AD9361 Reference Manual
UG-570
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
AD9361 Reference Manual
PL
EASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
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GENERAL INFORMATION
Complete specifications for the AD9361 part can be found in the AD9361 data sheet, which is available from Analog Devices, Inc., and
should be consulted in conjunction with this user guide when using the evaluation board.
Additional information about the AD9361 registers can be found in the AD9361 Register Map Reference Manual. While the register map
is provided as a convince and informational for those who want to understand the low level operation of the part, it is not recommended
to attempt to create your own software. Analog Devices provides complete drivers for the AD9361 for both bare metal/No-OS and
operating systems (Linux). The AD9361 and AD9364 share the same API. The AD9361 and AD9364 drivers can be found at:
• Linux wiki page
• No-OS wiki page
Support for these drivers can be found at:
• Linux engineer zone page
• No-OS engineer zone page
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TABLE OF CONTENTS
General Information ........................................................................ 1
Revision History ............................................................................... 4
Introduction ...................................................................................... 5
Terminology .................................................................................. 5
Register and Bit Syntax ................................................................ 5
Initialization and Calibration .......................................................... 6
Overview ........................................................................................ 6
Initalization Calibrations ............................................................. 7
BBPLL VCO Calibration ............................................................. 8
RF Synthesizer Charge Pump Calibration ................................ 8
RF Synthesizer VCO Calibration ............................................... 8
Baseband Rx Analog Filter Calibration ..................................... 9
Baseband Tx Analog Filter Calibration ................................... 10
Baseband Tx Secondary Filter .................................................. 11
Rx TIA Calibration Equations .................................................. 11
Rx ADC Setup ............................................................................. 11
Baseband DC Offset Calibration .............................................. 11
Baseband DC Offset Tracking .................................................. 11
RF DC Offset Calibration .......................................................... 12
Rx Quadrature Tracking Calibration ....................................... 13
Tx Quadrature Calibration ....................................................... 13
Reference Clock Requirements ..................................................... 14
Overview ...................................................................................... 14
DCXO Setup and Operation ..................................................... 14
Reference Clock Setup and Operation .................................... 15
Phase Noise Specification .......................................................... 15
RF and BBPLL Synthesizer ............................................................ 16
Overview ...................................................................................... 16
RFPLL Introduction ................................................................... 16
AD9361 PLL Architecture ......................................................... 16
Reference Block .......................................................................... 16
Main PLL Block .......................................................................... 17
Charge Pump Current ............................................................... 18
RFPLL Loop Filter ...................................................................... 18
VCO Configuration ................................................................... 18
VCO Calibration......................................................................... 18
VCO Vtune Measurement ......................................................... 18
Lock Detector .............................................................................. 18
Synthesizer Look Up Table ........................................................ 19
TDD Mode Faster Lock Times ................................................. 19
External LO ................................................................................. 19
Baseband PLL (BBPLL) ............................................................. 19
BBPLL VCO ................................................................................ 20
BBPLL Charge Pump ................................................................. 21
BBPLL Loop Filter ...................................................................... 21
Fast Lock Profiles ............................................................................ 22
Overview ..................................................................................... 22
Fast Lock Initial Wider BW Option ......................................... 22
Configuring and Using a Fast Lock Profile............................. 23
Fast Lock Pin Select ................................................................... 24
Enable State Machine Guide ......................................................... 25
Overview ..................................................................................... 25
ENSM State Definitions............................................................. 25
Modes of Operation ................................................................... 26
Sleep State .................................................................................... 30
Filter Guide...................................................................................... 31
Overview ..................................................................................... 31
Tx Signal Path ............................................................................. 31
Tx Digital Filter Blocks .............................................................. 31
Tx Analog Filter Blocks ............................................................. 32
Rx Signal Path ............................................................................. 33
Rx Analog Filter Blocks ............................................................. 33
Rx Digital Filter Blocks .............................................................. 33
Digital Rx Block Delay ............................................................... 34
Gain Control ................................................................................... 35
Overview ..................................................................................... 35
Gain Control Threshold Detectors .......................................... 36
LMT Overload Detector ............................................................ 36
ADC Overload Detector ........................................................... 36
Low Power Threshold ................................................................ 36
Average Signal Power ................................................................. 36
Settling Times ............................................................................. 37
Peak Overload Wait Time ......................................................... 37
Settling Delay .............................................................................. 37
Gain Table Overview ................................................................. 37
Full Table Mode .......................................................................... 37
Split Table Mode ......................................................................... 38
Digital Gain ................................................................................. 38
MGC Overview .......................................................................... 38
Slow Attack AGC Mode ............................................................ 40
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Slow Attack AGC Gain Update Time ....................................... 40
Overloads in Slow Attack AGC Mode ...................................... 41
Slow Attack AGC and Gain Tables ........................................... 41
Hybrid AGC Mode ..................................................................... 42
Fast Attack AGC Mode ............................................................... 42
State 0: RESET ............................................................................. 43
State 1: Peak Overload Detect ................................................... 43
State 2: Measure Power and Lock Level Gain Change ........... 44
State 3: Measure Power and Peak Overload Detect ................ 44
State 4: Unlock Gain ................................................................... 44
State 5: Gain Lock and Measure Power .................................... 45
Custom Gain Tables ........................................................................ 47
Overview ...................................................................................... 47
RF DC Cal Bit .............................................................................. 49
Maximum Full Table/LMT Table Index ................................... 49
External LNA ............................................................................... 49
Received Signal Strength Indicator (RSSI) .................................. 50
Overview ...................................................................................... 50
Mode Select and Measurement Duration ................................ 50
RSSI Weighting ............................................................................ 50
RSSI Delay and RSSI Wait .......................................................... 50
RSSI Preamble and RSSI Symbol .............................................. 51
RSSI RFIR ..................................................................................... 51
RSSI Gain Step Calibration ........................................................ 51
Transmit Power Control ................................................................. 55
Overview ...................................................................................... 55
Tx Attenuation Words ................................................................ 55
Attenuation Word Update Options .......................................... 55
Tx Power Monitor ........................................................................... 56
Overview ...................................................................................... 56
Tx Power Monitor Description ................................................. 56
Input Matching/Attenuation Network ..................................... 57
Tx Power Monitor Gain Control ............................................... 58
TPM Dynamic Range ................................................................. 59
Example of Tx Mon Configuration and Measurement of TPM
Transfer Function ........................................................................ 59
TPM Test Mode ........................................................................... 60
RF Port Interface ............................................................................. 61
Overview ...................................................................................... 61
Rx Signal Path Interface ............................................................. 62
Tx Signal Path Interface ............................................................. 69
Factory Calibrations ....................................................................... 71
Overview ...................................................................................... 71
Internal DCXO ............................................................................ 71
Tx RSSI (Tx Monitor) ................................................................. 71
Rx RSSI ......................................................................................... 71
Rx GM/LNA Gain Step Calibration ......................................... 72
Tx Power Out vs. Tx Attenuation and Tx Power Out vs.
Carrier Frequency ....................................................................... 72
Control Output ................................................................................ 73
Overview ...................................................................................... 73
Description of Control Output Signals .................................... 74
0x035 = 0x00 (Calibration Busy and Done) ............................ 74
0x035 = 0x01 (PLL Lock) ........................................................... 75
0x035 = 0x02 (Calibration Busy) .............................................. 75
0x035 = 0x03 (Rx Gain Control) .............................................. 75
0x035 = 0x04 (Rx Gain Control) .............................................. 76
0x035 = 0x05 (Rx Gain Control) .............................................. 76
0x035 = 0x06 (Rx Gain Control) .............................................. 76
0x035 = 0x07 (Rx Gain Control) .............................................. 76
0x035 = 0x08 (Rx Gain Control) .............................................. 76
0x035 = 0x09 (RxOn, TxOn, RSSI) .......................................... 77
0x035 = 0x0A (Digital Overflow) ............................................. 77
0x035 = 0x0B (Calibration and ENSM States) ........................ 77
0x035 = 0x0C (Gain Control) ................................................... 77
0x035 = 0x0D (Tx Quadrature and RF DC Calibration
Status) ........................................................................................... 78
0x035 = 0x0E (Rx Quadrature and BB DC Calibration
Status) ........................................................................................... 78
0x035 = 0x0F (Gain Control) .................................................... 78
0x035 = 0x10 (Gain Control and RSSI) ................................... 78
0x035 = 0x11 (AuxADC Digital Output) ................................ 78
0x035 = 0x12 (Gain Control, Power Word Ready)................. 78
0x035 = 0x13 (Gain Control, Power Word Ready)................. 79
0x035 = 0x14 (Digital Overflow) .............................................. 79
0x035 = 0x15 (DC Offset Tracking) ......................................... 79
0x035 = 0x16 (Gain Control) .................................................... 79
0x035 = 0x17 (Gain Control) .................................................... 80
0x035 = 0x18 (DC Offset Tracking, Power Word Ready) ..... 80
0x035 = 0x19 (Charge Pump Calibration States) ................... 80
0x035 = 0x1A (Rx VCO and ALC Calibration States) ........... 80
0x035 = 0x1B (Tx VCO and ALC Calibration States) ........... 80
0x035 = 0x1C (Rx VCO Calibration States) ............................ 80
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0x035 = 0x1D (Tx VCO Calibration States) ........................... 80
0x035 = 0x1E (Gain Control, Temp Sense Valid, AuxADC
Valid) ............................................................................................ 81
0x035 = 0x1F (Gain Control) .................................................... 81
AuxADC/AuxDAC/GPO/Temp Sensor ...................................... 82
Overview ...................................................................................... 82
AuxDAC ...................................................................................... 82
AuxADC ...................................................................................... 83
Internal Temperature Sensor .................................................... 84
General Purpose Output Control ............................................. 85
Baseband Synchronization ............................................................ 87
Overview ...................................................................................... 87
Multichip Synchronization ........................................................ 87
Procedure ..................................................................................... 88
Synchronization Verification .................................................... 89
Digital Interface Specification ....................................................... 90
Overview ...................................................................................... 90
CMOS Mode Data Path and Clock Signals ............................. 91
CMOS Maximum Clock Rates and Signal Bandwidths ........ 92
Single Port Half Duplex Mode (CMOS).................................. 93
Single Port TDD Functional Timing (CMOS) ....................... 94
Single Port Full Duplex Mode (CMOS) .................................. 97
Single Port FDD Functional Timing (CMOS) ....................... 99
Dual Port Half Duplex Mode (CMOS).................................. 100
Dual Port TDD Functional Timing (CMOS) ....................... 101
Dual Port Full Duplex Mode (CMOS) .................................. 103
Dual Port FDD Functional Timing (CMOS) ....................... 104
Data Bus Idle and Turnaround Periods (CMOS) ................ 105
Data Path Timing Parameters (CMOS) ................................ 105
LVDS Mode Data Path and Clock Signals ............................ 106
LVDS Mode Data Path Signals ............................................... 107
LVDS Maximum Clock Rates and Signal Bandwidths ....... 108
Dual Port Full Duplex Mode (LVDS) .................................... 109
Data Path Functional Timing (LVDS) ................................... 109
Data Path Timing Parameters (LVDS) .................................. 111
Serial Peripheral Interface (SPI) ............................................. 113
Additional Interface Signals .................................................... 116
Power Supply and Layout Guide ................................................ 117
Overview ................................................................................... 117
PCB Material And Stack Up Selection .................................. 117
RF Transmission Line Layout ................................................. 118
Fan-out and Trace Space Guidelines ..................................... 119
Component Placement and Routing Guidelines ................. 120
Power Management and System Noise Considerations ...... 120
Power Distributions for Different Power Supply Domains 124
Rx LO Frequency Deviations Due to Power Supply
Transients .................................................................................. 126
Related Links ................................................................................. 128
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Change to Table 50 ....................................................................... 108
3/14—Revision 0: Initial Version
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INTRODUCTION
TERMINOLOGY
AGC
Automatic gain control where an algorithm in the AD9361
controls the receive path gain.
BBP
Baseband processor (or digital baseband).
BB
Baseband. Baseband received signals are those that have already
been downconverted from RF. Baseband transmit signals are
those that have not yet been upconverted to RF.
BB DC Cal
Baseband DC calibration. An on-chip calibration that reduces
the DC power in the received data by adding digital correction
words to the data between the Half-Band 1 filter and the receive
FIR filter. See the Initialization and Calibration section for more
information.
BBP
Baseband processor (or, digital baseband).
Cal
Calibration.
DC
Literally direct current. In this document, DC refers to
undesired received power in the center of the complex received
baseband spectrum.
ENSM
Enable state machine. This on-chip state machine moves the
AD9361 through its states and it also controls other functions
within the AD9361. See the Enable State Machine Guide section
for more information.
FDD
Frequency division duplex in which transmit and receive signals
can be present at the same time but use different frequencies
LMT
LNA, mixer, TIA. LMT refers to the LMT gain table as well as
an analog peak detector that monitors the signal level at the
input of the analog LPF. See the Gain Control section for more
information.
LO
Local oscillator, which refers to the desired RF carrier frequency
for the receiver and the transmitter.
LPF
Low-pass filter, which refers to the third-order analog low-pass
filter preceding the receive ADC and following the transmit
DAC.
LUT
Look up table, several calibration and functions depend on
either reading or storing look up tables for future use.
MGC
Manual gain control where the BBP controls some or all of the
gain control parameters in the AD9361.
PLL
Phase locked loop. The AD9361 uses PLLs to generate the
various clock rates within the chip as well as the Tx and Rx LO
frequencies.
RF
Radio frequency.
RF DC Cal
Radio frequency DC calibration is an on-chip calibration that
reduces DC power in the received data by applying a compen-
sating voltage between the LNA and the mixer. See the
Initialization and Calibration section for more information.
TDD
Time division duplex in which transmit and receive signals can
be present on the same frequency but at different times.
VCO
A voltage controlled oscillator (VCO) is a circuit in which the
output frequency of the oscillator is controlled by an input
voltage level. These VCOs are part of the PLLs on the AD9361.
The AD9361 must calibrate the VCOs before the frequency they
produce is accurate and stable.
REGISTER AND BIT SYNTAX
When a register with absolute bit locations is described in this
user guide, the format is always in hex for the register and
[Dx:Dy] for the bits. This format is best described by an
example such as 0x016[D0], which equates to Register 0x016
(hex), and only the lowest bit of this register. Thus, the register
and the bit locations are specifically delineated.
When describing the value of just a few bits, the following
format is used: x’byyy.
where
x equals the number of bits described.
b indicates binary.
yyy represents three digital bits with values of 0 or 1.
As an example, if two bits equal 2’b01, then the LSB = 1 and the
next higher bit = 0.
Rev. A
