没有合适的资源？快使用搜索试试~ 我知道了~
ee240课程，基于斯坦福A Basic Introduction to the gm IDBased Design
需积分: 0 0 下载量 104 浏览量
20231207
17:43:56
上传
评论
收藏 3.27MB PDF 举报
温馨提示
试读
15页
ee240课程，基于斯坦福A Basic Introduction to the gm IDBased Design
资源推荐
资源详情
资源评论
A Basic Intro duction to the g
m
/I
D
Based Design
Methodology
0.1 Abstract
This article introduces the reader to the g
m
/I
D
based
design methodology, which is a way to help CMOS
analog circuit designers link physical transistor pa
rameters to small signal models. It is written at the
level of university students who are taking a ﬁrst
course on analog integrated circuits. It is also rel
evant to experienced engineers interested in a design
ﬂow that incorporates technology details early in the
design cycle and yields excellent agreement between
handcalculations and c ircuit simulations.
0.2 Introduction
Following perhaps a long road to maturity, CMOS
has become an excellent platform for analog circuit
design. Not only is it unrivaled in switching and
chargemode processing, but it beneﬁts from persis
tent process improvements fueled by the digital con
sumer marke t. Unfortunately, designers may ﬁnd it
very di±cult to take advantage of these strengths. A
primary reason for this is that CMOS behavior is hard
to predict without using very complex models, and
this complexity only worsens with technology scal
ing. Designers, incidentally under pressure to meet
deadlines, are forced to either incorporate complex
models into their hand calculations or spiral into a
Spiceintensive design loop. Neither of these strate
gies are as eÆective or pleasant as we would like.
My goal in this article is to introduce you to the
g
m
/I
D
based design methodology, which greatly im
proves the predictability of CMOS smallsignal be
havior without requiring complex equations. We will
deﬁne the ratio g
m
/I
D
in more detail later, but for
now, just think of it as a design variable that encap
sulates the biasing conditions of a MOS transistor.
Or, even more concisely:
g
m
/I
D
º bias point smallsignal model
Development of the methodology will involve several
steps. We will start with a very broad overview of
analog circuit design to see what problem it is that
we are attemping to s olve, and how it has been solved
in the past. I will then explain, at a qualitative level,
Figure 1: Lowlevel circuit implementation is often
more di±cult than higherlevel design.
why the g
m
/I
D
based approach is the bes t tool for
solving this problem. Next, we will rehash the en
tire discussion at a quantitave level. This will entail
a review of transistor operation and a chronological
development of the tools we have available. Finally,
we will close with a thorough design example.
0.3 The Big Picture
0.3.1 Analog Design Relies on Ab
straction
Fig. 1 shows several levels of abstraction in which we
can view an analog design. Thanks to abstractions,
engineers working at the higher levels can perform
analysis using linear SignalsandSytems theory. This
is the domain of ﬁlters, gain blocks, OpAmp circuits,
etc. The mathematics that govern this realm are el
egant, often with centuriesold roots. Consequently,
we have gotten very good at understanding how to
work with these blocks. Most engineering schools
send students through an entire battery of courses
that satisfactorily cover this area.
Descending to the lower levels, there is a diÆerent
story. While we ﬁnd it straightforward to build a
gainoftwo stage using an OpAmp, we ﬁnd it very
di±cult to build the OpAmp itself. How big should
each transistor be? How much bias current is needed?
These lowlevel decisions can be unclear, and there
are two big reasons why. First, transistor behavior
1
Figure 2: Smallsignal model of a transistor.
is nonlinear, and classical SignalsandSystems anal
yses fall apart when applied to nonlinear systems.
Second, technology advancements change the rules of
the game faster than we can make them. There are
no centuriesold roots here! As a result, we simply do
not have a nice set of transistor equations that is both
compact enough for hand calculations and accurate
enough to match Spice simulations.
0.3.2 Making LowLevel Design Man
ageable
We can make lowlevel design easier if we transform
transistors into SignalsandSystemsfriendly devices.
As you know, we do this by approximating each tran
sistor with a few ideal elements, collectively referred
to as a smallsignal model. Fig. 2 shows a basic and
familiar small signal model of a MOSFET. It also
highlights the translational role that g
m
/I
D
(or its
predecessor, V
ov
, another biasing variable) plays in
the design process. Of course, the drawback of using
smallsignal models is that they introduce errors, as
all approximations must. But that is far outweighed
by the beneﬁts of using SignalsandSystems tech
niques, without which we would not have concepts
like gain, bandwidth, frequency response, poles, and
zeros!
Fig. 3, then, is a good illustration of how the g
m
/I
D

based design methodology ﬁts into the big picture.
At the top is the abstract SignalsandSystems world,
where we are very comfortable. At the bottom are
physical transistors, which, in the end, must behave
the way we want them to. Sitting in the middle of all
this is g
m
/I
D
, an intermediate biasing variable that
bridges the abstracttophysical gap very well. Keep
this picture in mind as we c ontinue our discussion.
Figure 3: Small signal models allow us to use tran
sistors in a SignalsandSystems context.
0.3.3 Why g
m
/I
D
is Better than V
ov
V
ov
based design, which we will shortly cover in m ore
detail, long predates g
m
/I
D
based design. As we have
already hinted, both V
ov
and g
m
/I
D
are quantities
that tell you something about the bias point of a tran
sistor. So, how are these approaches diÆerent?
When CMOS designers cho ose to follow a V
ov
based
design strategy, they implicitely accept the validity
of the longchannel model. I am certain that you are
familiar with the longchannel model (we will also
review it in a later section). When we were ﬁrst
taught how to analyze a MOSFET, we were shown
a derivation of it using basic calculus. Unfortunately,
most of the assumptions that make the derivation so
clean are untrue for today’s s mall geometries. Conse
quently, the V
ov
based methodology no longer yields
circuits that behave as intended. In order to salvage
the model, designers have tried to patch it with short
channel eÆects and a variety of curveﬁtting terms
that are (sometimes only wishfully) based on diÆer
ent physical arguments. But in the end, V
ov
based
design only gets harder and less accurate.
Our new strategy, g
m
/I
D
based design, does not rely
on the validity of the longchannel model. In fact,
it does not rely on the validity of anything except
simulation. This methodoloy is lookuptablebased.
The underlying philosophy is that the equations gov
erning MOSFETs are so complex that we must get
2
Figure 4: Highlevel comparison of two popular de
sign methodologies.
rid of them in favor of a few tables or graphs. And
because these graphs are generated using device sim
ulations in Spice, they are much more acc urate than
the longchannel model could ever hope to be.
It is no stretch to say that most of us cringe a little at
the thought of using a lookup table. With the advent
of cheap and powerful computing, we electrical en
gineers have lost touch with ﬁlter tables, log tables,
trigonometric tables, and the like. But our current
equational exclusivity has been only a brief fad in
our industry. Just as vacuum tube circuit designers
once used (and still use!) tube curves, so we are redis
covering the value of tablebased design for situations
where it is the most e±cient means of ”computation.”
Fig. 4 compares V
ov
based design and g
m
/I
D
based
design in a sidebyside summary. In both cases, we
need physical information about the technology tar
get. After all, the capabilities of the target will ob
viously aÆect transistor performance greatly. In the
case of the longchannel model, the technology data
must be limited to only the barest of essentials, such
as µ and C
ox
, otherwise hand calculations become in
tractible. Consequently, initial designs may only get
within an order of magnitude until the designer gets a
”feel” for that process. Meanwhile, the g
m
/I
D
based
method utilizes complete Spice models from the tech
nology target and yields initial results that only re
quire minor twe aking.
0.4 The MoreDe tailed Picture
Now I want us to start over trying to solve the design
problem, but at a more quantitative level. We will
reach the same conclusion, of course, even though we
are taking a very diÆerent approach.
A First Attempt at TransistorLevel Design
How might an intelligentbutinexperienced engineer
go about designing a circuit? Of course, I have a
preferred method towards which I am working, but
it is certainly worthwhile to see if we can solve the
design problem without knowing the answer ahead of
time.
To b egin, le t us step back and ask, what will our
ﬁnished design look like? Or, what is aﬁnishedde
sign? In the context of this article, it is a netlist.
Ultimately we just want a ﬁle that contains spe ciﬁca
tions for all the transistors, resistors, capacitors, etc.,
and explains how they are all connected together. Of
course, in the real world, circuits must be fabricated,
and designers must be wary of the limitations of simu
lation itself, and how well it agrees with actual mea
sured performance, but those concerns are beyond
our scope here.
If our end goal is a netlist, why not start with the
netlist and work backwards? What kinds of informa
tion do we need in order to ”ﬁll in the blanks?” For
reference, here is a line that instantiates a transistor
in Hspice:
M1 drn gat src blk nchmodel L=0.18u W=10u
Well, which blanks can we ﬁll in? Put another way,
how do we design a transistor? Obviously, V
T
, µ, C
ox
,
and other familiar transistor quantities are not among
the parameters we get to specify. In fact, apart from
the terminal connections, it looks like we only get to
choose W and L.
Is that all there is to it? Is circuit design just a matter
of deciding how big each transistor is? Well, yes and
no. With the exception of some advanced options
(such as source or drain sharing, or multiﬁngered
gates), W and L really are the only transistor charac
teristics that you get to explicitely specify. You hook
them together, size them correctly, and you almost
have the whole thing. Really!
One p ossible design method, then, might be to just
use W and L directly as design variables. This pro
cess would be something like the following:
3
剩余14页未读，继续阅读
资源评论
阳眀芓
 粉丝: 61
 资源: 1
上传资源 快速赚钱
 我的内容管理 展开
 我的资源 快来上传第一个资源
 我的收益 登录查看自己的收益
 我的积分 登录查看自己的积分
 我的C币 登录后查看C币余额
 我的收藏
 我的下载
 下载帮助
安全验证
文档复制为VIP权益，开通VIP直接复制
信息提交成功