瑞萨RA6M5实现DMAC存储器到存储器传输（FSP库驱动）.zip

FSP Configuration Board "Custom User Board (Any Device)" R7FA6M5BH3CFC part_number: R7FA6M5BH3CFC rom_size_bytes: 2097152 ram_size_bytes: 524288 data_flash_size_bytes: 8192 package_style: LQFP package_pins: 176 RA6M5 series: 6 RA6M5 Family Security: Exceptions: Exception Response: Non-Maskable Interrupt Security: Exceptions: BusFault, HardFault, and NMI Target: Secure State Security: System Reset Request Accessibility: Secure State Security: Exceptions: Prioritize Secure Exceptions: Disabled Security: Cache Accessibility: Both Secure and Non-Secure State Security: System Reset Status Accessibility: Both Secure and Non-Secure State Security: Battery Backup Accessibility: Both Secure and Non-Secure State Security: SRAM Accessibility: SRAM Protection: Both Secure and Non-Secure State Security: SRAM Accessibility: SRAM ECC: Both Secure and Non-Secure State Security: SRAM Accessibility: Standby RAM: Regions 7-0 are all Secure. Security: BUS Accessibility: Bus Security Attribution Register A: Both Secure and Non-Secure State Security: BUS Accessibility: Bus Security Attribution Register B: Both Secure and Non-Secure State Startup C-Cache Line Size: 32 Bytes OFS0 register settings: Independent WDT: Start Mode: IWDT is Disabled OFS0 register settings: Independent WDT: Timeout Period: 2048 cycles OFS0 register settings: Independent WDT: Dedicated Clock Frequency Divisor: 128 OFS0 register settings: Independent WDT: Window End Position: 0% (no window end position) OFS0 register settings: Independent WDT: Window Start Position: 100% (no window start position) OFS0 register settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled OFS0 register settings: Independent WDT: Stop Control: Stop counting when in Sleep, Snooze mode, or Software Standby OFS0 register settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode) OFS0 register settings: WDT: Timeout Period: 16384 cycles OFS0 register settings: WDT: Clock Frequency Division Ratio: 128 OFS0 register settings: WDT: Window End Position: 0% (no window end position) OFS0 register settings: WDT: Window Start Position: 100% (no window start position) OFS0 register settings: WDT: Reset Interrupt Request: Reset OFS0 register settings: WDT: Stop Control: Stop counting when entering Sleep mode OFS1 register settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset OFS1 register settings: Voltage Detection 0 Level: 2.80 V OFS1 register settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset Block Protection Settings (BPS): BPS0: Block Protection Settings (BPS): BPS1: Block Protection Settings (BPS): BPS2: Permanent Block Protection Settings (PBPS): PBPS0: Permanent Block Protection Settings (PBPS): PBPS1: Permanent Block Protection Settings (PBPS): PBPS2: Dual Bank Mode: Disabled Clocks: HOCO FLL Function: Disabled Main Oscillator Wait Time: 8163 cycles RA Common Main stack size (bytes): 0x400 Heap size (bytes): 0x1000 MCU Vcc (mV): 3300 Parameter checking: Disabled Assert Failures: Return FSP_ERR_ASSERTION Error Log: No Error Log Clock Registers not Reset Values during Startup: Disabled Main Oscillator Populated: Populated PFS Protect: Enabled C Runtime Initialization : Enabled Early BSP Initialization : Disabled Main Oscillator Clock Source: Crystal or Resonator Subclock Populated: Populated Subclock Drive (Drive capacitance availability varies by MCU): Standard/Normal mode Subclock Stabilization Time (ms): 1000 Clocks XTAL 24000000Hz HOCO 20MHz PLL Src: XTAL PLL Div /3 PLL Mul x25.0 PLL2 Disabled PLL2 Div /2 PLL2 Mul x20.0 Clock Src: PLL CLKOUT Disabled UCLK Disabled OCTASPICLK Disabled CANFDCLK Disabled ICLK Div /1 PCLKA Div /2 PCLKB Div /4 PCLKC Div /4 PCLKD Div /2 BCLK Div /2 BCLK/2 FCLK Div /4 CLKOUT Div /1 UCLK Div /5 OCTASPICLK Div /1 CANFDCLK Div /6 Pin Configurations R7FA6M5BH3CFC.pincfg -> g_bsp_pin_cfg AVCC0 155 ANALOG0_AVCC0 - - - - - - - - IO "Read only" - AVCCUSBHS 26 USB_HS0_AVCC_USBHS - - - - - - - - IO "Read only" - AVSS0 156 ANALOG0_AVSS0 - - - - - - - - IO "Read only" - AVSSUSBHS 28 USB_HS0_AVSS_USBHS - - - - - - - - IO "Read only" - P000 169 - - - - Disabled - - "ADC0: AN000; ADC1: AN100; ICU0: IRQ06" - None - - P001 168 - - - - Disabled - - "ADC0: AN001; ADC1: AN101; ICU0: IRQ07" - None - - P002 167 - - - - Disabled - - "ADC0: AN002; ADC1: AN102; ICU0: IRQ08" - None - - P003 166 - - - - Disabled - - "ADC0: AN003" - None - - P004 165 - - - - Disabled - - "ADC0: AN004; ICU0: IRQ09" - None - - P005 164 - - - - Disabled - - "ADC0: AN005; ICU0: IRQ10" - None - - P006 163 - - - - Disabled - - "ADC0: AN006; ICU0: IRQ11" - None - - P007 162 - - - - Disabled - - "ADC0: AN007" - None - - P008 161 - - - - Disabled - - "ADC0: AN008; ICU0: IRQ12" - None - - P009 160 - - - - Disabled - - "ADC0: AN009; ICU0: IRQ13" - None - - P010 159 - - - - Disabled - - "ADC0: AN010; ICU0: IRQ14" - None - - P014 152 - - - - Disabled - - "ADC0: AN012; DAC0: DA0" - None - - P015 151 - - - - Disabled - - "ADC0: AN013; DAC1: DA1; ICU0: IRQ13" - None - - P100 132 - - - - Disabled - - "AGT0: AGTIO0; BUS_ASYNCH0: D00; GPT_POEG0: GTETRGA; GPT5: GTIOC5B; ICU0: IRQ02; OSPI0: OMSCLK; QSPI0: QSPCLK; SCI0: RXD0; SCI0: SCL0; SCI1: SCK1; SPI1: MISOB" - None - - P101 131 - - - - Disabled - - "AGT0: AGTEE0; BUS_ASYNCH0: D01; GPT_POEG1: GTETRGB; GPT5: GTIOC5A; ICU0: IRQ01; OSPI0: OMSIO7; QSPI0: QIO1; SCI0: SDA0; SCI0: TXD0; SCI1: CTSRTS1; SPI1: MOSIB" - None - - P102 130 - - - - Disabled - - "ADC0: ADTRG0; AGT0: AGTO0; BUS_ASYNCH0: D02; CAN0: CRX0; GPT_OPS0: GTOWLO; GPT2: GTIOC2B; OSPI0: OMSIO1; QSPI0: QIO0; SCI0: SCK0; SPI1: RSPCKB" - None - - P103 129 - - - - Disabled - - "AGT2: AGTIO2; BUS_ASYNCH0: D03; CAN0: CTX0; GPT_OPS0: GTOWUP; GPT2: GTIOC2A; OSPI0: OMSIO6; QSPI0: QIO3; SCI0: CTSRTS0; SPI1: SSLB0" - None - - P104 128 - - - - Disabled - - "AGT2: AGTEE2; BUS_ASYNCH0: D04; GPT_POEG1: GTETRGB; GPT1: GTIOC1B; ICU0: IRQ01; OSPI0: OMDQS; QSPI0: QIO2; SCI8: RXD8; SCI8: SCL8; SPI1: SSLB1" - None - - P105 127 - - - - Disabled - - "AGT2: AGTO2; BUS_ASYNCH0: D05; GPT_POEG0: GTETRGA; GPT1: GTIOC1A; ICU0: IRQ00; OSPI0: OMSIO5; SCI8: SDA8; SCI8: TXD8; SPI1: SSLB2" - None - - P106 126 - - - - Disabled - - "AGT0: AGTOB0; BUS_ASYNCH0: D06; GPT8: GTIOC8B; OSPI0: OMSIO0; SCI8: SCK8; SPI1: SSLB3" - None - - P107 125 - - - - Disabled - - "AGT0: AGTOA0; BUS_ASYNCH0: D07; GPT8: GTIOC8A; OSPI0: OMSIO3; SCI8: CTSRTS8" - None - - P108 89 DEBUG0_SWDIO - Low - "Peripheral mode" CMOS None "AGT3: AGTOA3; DEBUG0: SWDIO; DEBUG0: TMS; GPT_OPS0: GTOULO; GPT0: GTIOC0B; SCI9: CTSRTS9; SPI0: SSLA0" - IO - - P109 90 - - - - Disabled - - "AGT3: AGTOB3; CAN1: CTX1; CGC0: CLKOUT; DEBUG0: TDO; DEBUG0: TRACESWO; GPT_OPS0: GTOVUP; GPT1: GTIOC1A; SCI9: SDA9; SCI9: TXD9; SPI0: MOSIA" - None - - P110 91 - - - - Disabled - - "AGT3: AGTEE3; CAN1: CRX1; DEBUG0: TDI; GPT_OPS0: GTOVLO; GPT1: GTIOC1B; ICU0: IRQ03; SCI2: CTSRTS2; SCI9: RXD9; SCI9: SCL9; SPI0: MISOA" - None - - P111 92 - - - - Disabled - - "AGT5: AGTOA5; BUS_ASYNCH0: A05; GPT3: GTIOC3A; ICU0: IRQ04; SCI2: SCK2; SCI9: SCK9; SPI0: RSPCKA" - None - - P112 93 - - - - Disabled - - "AGT5: AGTOB5; BUS_ASYNCH0: A04; GPT3: GTIOC3B; OSPI0: OMCS1; QSPI0: QSSL; SCI1: SCK1; SCI2: SDA2; SCI2: TXD2; SPI0: SSLA0; SSI0: SSIBCK0" - None - - P113 94 - - - - Disabled - - "AGT5: AGTEE5; BUS_ASYNCH0: A03; GPT2: GTIOC2A; SCI2: RXD2; SCI2: SCL2; SSI0: SSILRC