XC7K325T驱动程序，Verilog HDL实现。 项目代码可顺利编译运行~~
XC7K325T实现DDR3读写数据【Verilog HDL驱动】 （677个子文件） 
__synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B __synthesis_is_complete__ 0B _info 101KB _info 155B _info 155B _vmake 29B xsim_run.bat 3KB xsim_run.bat 3KB simulate.bat 807B compile.bat 801B runme.bat 305B runme.bat 305B runme.bat 305B runme.bat 305B runme.bat 305B runme.bat 305B top_ddr3_rw.bit 10.91MB waveform.csv 258KB waveform.csv 257KB waveform.csv 43KB waveform.csv 34KB ssm.db 598B xsim.dbg 6KB xsim.dbg 6KB xsim.dbg 2KB xsim.dbg 2KB top_ddr3_rw_routed.dcp 11.16MB top_ddr3_rw_physopt.dcp 9.52MB top_ddr3_rw_placed.dcp 9.52MB top_ddr3_rw_opt.dcp 7.24MB mig_7series_0.dcp 4.93MB mig_7series_0.dcp 4.93MB wr_fifo.dcp 375KB wr_fifo.dcp 374KB wr_fifo.dcp 374KB rd_fifo.dcp 358KB rd_fifo.dcp 356KB rd_fifo.dcp 356KB top_ddr3_rw.dcp 176KB clk_wiz_0.dcp 12KB clk_wiz_0.dcp 12KB clk_wiz_0.dcp 12KB waveform.dmp 178KB waveform.dmp 158KB waveform.dmp 158KB waveform.dmp 75KB tb_top_ddr3_rw_compile.do 10KB compile.do 9KB compile.do 9KB compile.do 9KB compile.do 9KB sim.do 7KB sim.do 7KB tb_top_ddr3_rw_simulate.do 629B simulate.do 371B tb_top_ddr3_rw_wave.do 347B simulate.do 300B simulate.do 300B simulate.do 255B elaborate.do 217B simulate.do 117B wave.do 32B wave.do 32B simulate.do 11B exempt2wghih 1.5MB exemptszxir9 768B exemptv18rze 26KB xil_txt.in 1KB xil_txt.in 1KB modelsim.ini 172KB modelsim.ini 172KB xsim.ini 29KB vivado.jou 990B vivado.jou 962B vivado.jou 948B vivado.jou 948B vivado.jou 945B vivado.jou 940B ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB ISEWrap.js 8KB rundef.js 1KB rundef.js 1KB rundef.js 1KB rundef.js 1KB rundef.js 1KB rundef.js 1KB .ila_0.xcix.lock 0B .rd_fifo.xcix.lock 0B .wr_fifo.xcix.lock 0B .clk_wiz_0.xcix.lock 0B .ila_1.xcix.lock 0B simulate.log 54.68MB compile.log 246KB共 677 条
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