################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA MPSoC_XCZU2EG控制LED灯闪烁(Vivado HLS实现).zip
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FPGA MPSoC_XCZU2EG控制LED灯闪烁(Vivado HLS实现).zip (329个子文件)
a.g.0 119KB
__synthesis_is_complete__ 0B
led_twinkle.adb 56KB
led_twinkle.bind.adb 40KB
led_twinkle.sched.adb 33KB
autopilot.apfmapping 350B
vivado_hls.app 457B
solution1.aps 4KB
.automg_exit 32B
.autopilot_exit 22B
ipi_example.bat 451B
pack.bat 375B
runme.bat 229B
runme.bat 229B
a.o.3.bc 3KB
a.o.1.tmp.bc 2KB
a.o.2.bc 2KB
a.g.2.bc 2KB
a.g.2.prechk.bc 2KB
led_twinkle.g.bc 2KB
a.pp.bc 2KB
led_twinkle.bc 2KB
a.g.bc 2KB
a.pp.0.bc 2KB
a.g.0.bc 2KB
a.o.1.bc 2KB
a.g.1.bc 2KB
useless.bc 1000B
system.bd 4KB
system_wrapper.bit 5.31MB
system.bxml 4KB
led_twinkle.pragma.1.c 239KB
led_twinkle.pragma.2.c 239KB
led_twinkle.pp.0.c 239KB
led_twinkle.pragma.0.c 239KB
led_twinkle.c 279B
led_twinkle.cpp 6KB
hls_design_meta.cpp 314B
.cproject 28KB
system_wrapper_routed.dcp 425KB
system_wrapper_physopt.dcp 419KB
system_wrapper_placed.dcp 417KB
system_wrapper_opt.dcp 396KB
system_wrapper.dcp 34KB
system_led_twinkle_0_0.dcp 17KB
system_util_vector_logic_0_0.dcp 6KB
solution1.directive 90B
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
simulate.do 333B
simulate.do 325B
simulate.do 325B
elaborate.do 205B
simulate.do 189B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
dsp_style 7B
run.f 968B
run.f 948B
solution1.funcunit 588B
a.g 119KB
led_twinkle.h 2KB
hls_design_meta.h 408B
usage_statistics_webtalk.html 33KB
usage_statistics_ext_labtool.html 3KB
system_wrapper.hwdef 9KB
system.hwdef 9KB
system.hwh 40KB
.xsim_webtallk.info 59B
xsim.ini 26KB
vivado.jou 845B
vivado.jou 841B
vivado.jou 682B
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
solution1_data.json 4KB
all.directive.json 10B
led_twinkle_hls.Release.launch 2KB
led_twinkle_hls.Debug.launch 2KB
autopilot.flow.log 105KB
runme.log 35KB
runme.log 32KB
solution1.log 24KB
vivado_hls.log 1KB
vivado.log 957B
labtool_webtalk.log 744B
autoimpl.log 523B
led_twinkle_ip_test.lpr 343B
elab.opt 210B
vivado.pb 49KB
place_design.pb 20KB
route_design.pb 15KB
opt_design.pb 12KB
共 329 条
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