/*****************************************************************************
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
* 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but
* cacheable regions
* Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
* generated by the cpu driver, for enabling caches
* 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/
* write-thru caches
* 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC
* Updated the MMU table to mark OCM in high address space
* as inner cacheable and reserved space as Invalid
* 3.03a sdm 08/20/11 Changes to support FreeRTOS
* Updated the MMU table to mark upper half of the DDR as
* non-cacheable
* Setup supervisor and abort mode stacks
* Do not initialize/enable L2CC in case of AMP
* Initialize UART1 for 9600bps in case of AMP
* 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC
* in case of AMP
* 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event
* counters
* 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include
* xparameters.h file for CR630532 - Xil_DCacheFlush()/
* Xil_DCacheFlushRange() functions in standalone BSP v3_02a
* for MicroBlaze will invalidate data in the cache instead
* of flushing it for writeback caches
* 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
* Remove redundant dsb/dmb instructions in cache maintenance
* APIs
* Remove redundant dsb in mcr instruction
* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
* 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl in xparameters.h. Update the gcc/translationtable.s
* for the QSPI complete address range - DT644567
* Removed profile directory for armcc compiler and changed
* profiling setting to false in standalone_v2_1_0.tcl file
* Deleting boot.S file after preprocessing for armcc compiler
* 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
* invalidate the caches before enabling back the MMU and
* D cache.
* 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file
* xil_mmu.c. Now we invalidate UTLB, Branch predictor
* array, flush the D-cache before changing the attributes
* in translation table. The user need not call Xil_DisableMMU
* before calling Xil_SetTlbAttributes.
* 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
* sgd initialization is present. Changes for this were done in
* uart.c and xil-crt0.s.
* Made changes in xil_io.c to use volatile pointers.
* Made changes in xil_mmu.c to correct the function
* Xil_SetTlbAttributes.
* Changes are made xil-crt0.s to initialize the static
* C++ constructors.
* Changes are made in boot.s, to fix the TTBR settings,
* correct the L2 Cache Auxiliary register settings, L2 cache
* latency settings.
* 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
* sgd usleep.c to use global timer instead of CP15.
* Made changes in cortexa9/gcc/translation_table.s to map
* the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/xil-crt0.s to initialize
* the global timer.
* Made changes in cortexa9/armcc/boot.S to initialize
* the global timer.
* Made changes in cortexa9/armcc/translation_table.s to
* map the peripheral devices as shareable device memory.
* Made changes in cortexa9/gcc/boot.S to optimize the
* L2 cache settings. Changes the section properties for
* ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
* and cortexa9/gcc/translation_table.S.
* Made changes in cortexa9/xil_cache.c to change the
* cache invalidation order.
* 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove
* compilation/linking issues for C++ compiler.
* Made changes in mb_interface.h to remove compilation/
* linking issues for C++ compiler.
* Added macros for swapb and swaph microblaze instructions
* mb_interface.h
* Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
* for CortexA9.
* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
* 3.07a asa 08/31/12 Added xil_printf.h include
* 3.07a sgd 09/18/12 Corrected the L2 cache enable settings
* Corrected L2 cache sequence disable sequence
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option
* 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for
* irq/fiq handling.
* Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
* fixes the CR #692094.
* 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
* 3.10a srt 04/18/13 Implemented ARM Erratas.
* Cortex A9 Errata - 742230, 743622, 775420, 794073
* L2Cache PL310 Errata - 588369, 727915, 759370
* Please refer to file 'xil_errata.h' for errata
* description.
* 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
* cache APIs were corresponding to only Layer 1 cache
* memories. New APIs were now added and the existing cache
* related APIs were changed to provide a uniform interface
* to flush/invalidate/enable/disable the complete cache
* system which includes both L1 and L2 caches. The changes
* for these were done in:
* src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
* files.
* Four new files were added for supporting L2 cache. They are:
* microblaze_flush_cache_ext.S-> Flushes L2 cache
* microblaze_flush_cache_ext_range.S -> Flushes a range of
* memory in L2 cache.
* microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
* microblaze_invalidate_cache_ext_range -> Invalidates a
* range of memory in L2 cache.
* These changes are done to implement PR #697214.
* 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
* fix the CR #706464. L2 cache disabling happens independent
* of L1 data cache disable operation. Changes are done in the
* same file in cache handling APIs to do a L2 cache sync
* (poll reg7_?cache_?sync). This fixes CR #700542.
* 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested
* interrupts for ARM. These are done to fix the CR#699680.
* 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach
* sync operation. This fixes the CR# 716781.
* 3.11a asa 09/07/13 Updated armcc specific BSP files to have proper support
* for armcc toolchain.
* Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
* fix issues related to NEON context saving. The assembly
* routines for IRQ and FIQ handling are modified.
* Deprecated the older BSP (3.10a).
* 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
* various potential issues. Made changes i
没有合适的资源?快使用搜索试试~ 我知道了~
FPGA MPSoC_XCZU2CG实现PS端RTC定时器中断(VITIS实现).zip
共2000个文件
h:716个
c:392个
o:245个
1.该资源内容由用户上传,如若侵权请联系客服进行举报
2.虚拟产品一经售出概不退款(资源遇到问题,请及时私信上传者)
2.虚拟产品一经售出概不退款(资源遇到问题,请及时私信上传者)
版权申诉
0 下载量 76 浏览量
2023-04-26
18:11:23
上传
评论
收藏 41.17MB ZIP 举报
温馨提示
FPGA MPSoC XCZU2CG、XCZU2EG和XCZU4EV驱动程序。 基于VITIS实现。 项目代码可顺利编译运行~
资源推荐
资源详情
资源评论
收起资源包目录
FPGA MPSoC_XCZU2CG实现PS端RTC定时器中断(VITIS实现).zip (2000个子文件)
002946629e8c001d1527d94e214d3c19 6KB
005cfff09b8c001d1527d94e214d3c19 2KB
00a68fdc998c001d1527d94e214d3c19 2KB
00c02e179c8c001d1527d94e214d3c19 2KB
00ee93f79b8c001d1527d94e214d3c19 2KB
10297a5c9c8c001d1527d94e214d3c19 1KB
20886e179c8c001d1527d94e214d3c19 1KB
209541f19b8c001d1527d94e214d3c19 2KB
20a224f29b8c001d1527d94e214d3c19 1KB
20a81d649e8c001d1527d94e214d3c19 2KB
20b31e679e8c001d1527d94e214d3c19 2KB
20df775c9c8c001d1527d94e214d3c19 1KB
3062b13d9e8c001d1527d94e214d3c19 2KB
40b873179c8c001d1527d94e214d3c19 1KB
40c32a509c8c001d1527d94e214d3c19 2KB
50281f679e8c001d1527d94e214d3c19 1KB
50993ff19b8c001d1527d94e214d3c19 1KB
50a9b9f89b8c001d1527d94e214d3c19 1KB
606d1a679e8c001d1527d94e214d3c19 2KB
6090365c9c8c001d1527d94e214d3c19 2KB
70477f4c9c8c001d1527d94e214d3c19 6KB
7048fd669e8c001d1527d94e214d3c19 2KB
706489dc998c001d1527d94e214d3c19 1KB
7079d4f79b8c001d1527d94e214d3c19 2KB
70d3f1379e8c001d1527d94e214d3c19 6KB
80096fdd998c001d1527d94e214d3c19 1KB
801c4b509c8c001d1527d94e214d3c19 1KB
802652179c8c001d1527d94e214d3c19 2KB
8068923d9e8c001d1527d94e214d3c19 2KB
80f80f3a9e8c001d1527d94e214d3c19 2KB
904cb23d9e8c001d1527d94e214d3c19 1KB
90e706509c8c001d1527d94e214d3c19 2KB
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
libxil.a 4.41MB
libxil.a 3.54MB
libxil.a 2.13MB
libxil.a 2.13MB
libgcc.a 1.73MB
libc.a 1.02MB
libxilsecure.a 588KB
libxilsecure.a 587KB
libxilskey.a 577KB
libm.a 576KB
libxilpm.a 574KB
libxilfpga.a 296KB
libxilffs.a 48KB
libgloss.a 22KB
a031b5f79b8c001d1527d94e214d3c19 2KB
.analytics 2KB
assumedExternalFilesCache 4B
b0207e5c9c8c001d1527d94e214d3c19 1KB
b06165dc998c001d1527d94e214d3c19 2KB
b0a4d2f79b8c001d1527d94e214d3c19 1KB
b0af46509c8c001d1527d94e214d3c19 1KB
b0bf18679e8c001d1527d94e214d3c19 1KB
runme.bat 229B
runme.bat 229B
runme.bat 229B
design_1.bd 82KB
design_1_wrapper.bif 225B
system.bif 223B
BOOT.BIN 5.44MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1.bxml 3KB
ffunicode.c 1.87MB
psu_init.c 628KB
psu_init.c 628KB
psu_init.c 628KB
psu_init.c 628KB
psu_init.c 628KB
psu_init_gpl.c 628KB
psu_init_gpl.c 628KB
psu_init_gpl.c 628KB
psu_init_gpl.c 628KB
ff.c 223KB
xfsbl_ddr_init.c 214KB
xilskey_eps_zynqmp.c 102KB
xilfpga_pcap.c 75KB
pm_clock.c 70KB
xsysmonpsu.c 69KB
xsysmonpsu.c 69KB
xsysmonpsu.c 69KB
pm_api_sys.c 64KB
xaxipmon.c 63KB
xaxipmon.c 63KB
xaxipmon.c 63KB
pm_core.c 60KB
pm_ddr.c 58KB
xfsbl_initialization.c 56KB
xfsbl_partition_load.c 52KB
pm_reset.c 49KB
xsecure.c 48KB
xsecure.c 48KB
xsecure_aes.c 46KB
共 2000 条
- 1
- 2
- 3
- 4
- 5
- 6
- 20
资源评论
不脱发的程序猿
- 粉丝: 24w+
- 资源: 5837
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功