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## liability) for any loss or damage of any kind or nature
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###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 4.2
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
## Cadence IES, and Synopsys VCS
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
## Example Design" directory
## Reference :
## Revision History:
###############################################################################
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
Vivado Simulator, IES and VCS. These scripts are valid only for running
simulations for "Open IP Example Design"
1. How to run simulations in Modelsim/QuestaSim simulator
A) sim.do File :
a) The 'sim.do' file has commands to compile and simulate memory
interface design and run the simulation for specified period of time.
b) It has the syntax to Map the required libraries (unisims_ver,
unisim and secureip). The libraries should be mapped using
the following command
vmap unisims_ver <unisims_ver lib path>
vmap unisim <unisim lib path>
vmap secureip <secureip lib path>
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
c) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim/QuestaSim simulation:
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
b) Change the present working directory path to the sim folder.
In Transcript window, at Modelsim/QuestaSim prompt, type the following
command to change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim/QuestaSim prompt, type the following command:
do sim.do
d) To exit simulation, type the following command at Modelsim/QuestaSim
prompt:
quit -f
e) Verify the transcript file for the memory transactions.
2. How to run simulations in Vivado simulator
A) Following files are provided :
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
MicroSoft Windows environment.
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
Linux environment.
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
simulate memory interface design and run the simulation for specified
period of time.
d) xsim_options.tcl file has commands to add waveforms and simulation
period.
e) xsim_files.prj file has list of rtl files for simulating the design.
f) $XILINX_VIVADO environment variable must be set in order to compile
glbl.v file
B) Steps to run the Vivado Simulator simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using xsim_run.sh file under Linux environment and
xsim_run.bat under MicroSoft Windows environment.
c) Verify the transcript file for the memory transactions.
3. How to run Cadence IES Simulations
A) ies_run.sh File :
a) The "ies_run.sh" file contains the commands for simulation of the
hdl files.
b) Libraries must be mapped before running simulations. Following
procedure must be followed to before running simulations
1. Create two files named cds.lib and hdl.var in this directory
2. Create a directory 'worklib' in same directory.
mkdir worklib
3. Add following lines in the cds.lib file to map Xilinx libraries
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
DEFINE worklib ./worklib
4. ATTENTION: In above lines replace the path for libraries as per your
compiled Xilinx libraries directory
5. ATTENTION: Add the lines in the same order given above
6. Please make sure you need to map all Xilinx libraries mentioned above
7. Save and close the cds.lib file
Also, $XILINX_VIVADO environment variable must be set in order to
compile glbl.v file and the above mentioned library files
B) Steps to run the IES simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using ies_run.sh file. Type the following command:
./ies_run.sh
c) Verify the ies_sim.log file for the memory transactions.
4. How to run Synopsys VCS Simulations
A) vcs_run.sh Fi
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FPGA XC7A35T驱动RGB LCD彩条显示(Microblaze实现) (1703个子文件)
00ffe440f07f001b1203b5a5760ab7a0 2KB
1053b0b8df7f001b1868c2b426956f57 2KB
10d62cb9df7f001b1868c2b426956f57 2KB
2018d940f07f001b1203b5a5760ab7a0 1KB
2019593df07f001b1203b5a5760ab7a0 322KB
202d9740f07f001b1203b5a5760ab7a0 2KB
206be040f07f001b1203b5a5760ab7a0 2KB
20a7c2afe57f001b108fe8509f8572de 2KB
20ccdbf8977d001b16abecb95cd31769 1KB
30728d13987d001b16abecb95cd31769 2KB
30eccc13987d001b16abecb95cd31769 1KB
40a9d9f8977d001b16abecb95cd31769 2KB
5033e840f07f001b1203b5a5760ab7a0 1KB
50c2e540f07f001b1203b5a5760ab7a0 1KB
50d3fd3ff07f001b1203b5a5760ab7a0 2KB
60136db9df7f001b1868c2b426956f57 1KB
608e43787e80001b1a9e90631800a557 2KB
60b4c5afe57f001b108fe8509f8572de 1KB
7035b7afe57f001b108fe8509f8572de 1KB
70fe76b9df7f001b1868c2b426956f57 2KB
80154013987d001b16abecb95cd31769 2KB
8073c8afe57f001b108fe8509f8572de 1KB
80a6cae67d80001b1a9e90631800a557 322KB
903850787e80001b1a9e90631800a557 1KB
90b8d213987d001b16abecb95cd31769 1KB
__synthesis_is_complete__ 0B
libgcc.a 1.77MB
libgcc.a 1.77MB
libgcc.a 1.64MB
libc.a 1.23MB
libc.a 1.23MB
libc.a 1.11MB
libm.a 722KB
libm.a 722KB
libm.a 683KB
libxil.a 600KB
libxil.a 600KB
libxil.a 80KB
libgloss.a 22KB
libgloss.a 22KB
libgloss.a 21KB
a07bf8777e80001b1a9e90631800a557 2KB
.analytics 6KB
assumedExternalFilesCache 4B
b011a8777e80001b1a9e90631800a557 2KB
b07573afe57f001b108fe8509f8572de 2KB
b0cadc13987d001b16abecb95cd31769 1KB
b0ed7eb9df7f001b1868c2b426956f57 1KB
xsim_run.bat 3KB
runme.bat 229B
runme.bat 229B
system.bd 58KB
system_wrapper.bif 70B
system_wrapper.bin 2.09MB
system_wrapper.bit 2.09MB
system_wrapper.bit 2.09MB
system_wrapper.bit 2.09MB
system_wrapper.bit 2.09MB
system_wrapper.bit 2.09MB
system_wrapper.bit 2.09MB
system_wrapper.bit 2.09MB
system_wrapper.bit 2.09MB
system_wrapper_bd.bmm 6KB
system.bmm 520B
system.bmm 520B
system.bxml 15KB
xuartlite.c 23KB
xuartlite.c 23KB
xil_testmem.c 20KB
xil_testmem.c 20KB
xbram_selftest.c 17KB
xbram_selftest.c 17KB
xil_misc_psreset_api.c 16KB
xil_misc_psreset_api.c 16KB
_profile_timer_hw.c 12KB
_profile_timer_hw.c 12KB
xil_printf.c 12KB
xil_printf.c 11KB
xil_util.c 11KB
xuartlite_intr.c 11KB
xuartlite_intr.c 11KB
xil_testcache.c 10KB
xil_testcache.c 9KB
xil_testio.c 8KB
xbram_intr.c 8KB
microblaze_sleep.c 8KB
xil_testio.c 8KB
xbram_intr.c 8KB
microblaze_sleep.c 8KB
xio.c 7KB
xil_exception.c 7KB
xio.c 7KB
xil_exception.c 7KB
xbram.c 5KB
xplatform_info.c 5KB
xplatform_info.c 5KB
xbram.c 5KB
xil_assert.c 5KB
main.c 5KB
xuartlite_sinit.c 5KB
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