################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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ZYNQ 7020驱动OV5640采集UDP通信上传视频(FPGA驱动).zip
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ZYNQ 7020驱动OV5640采集UDP通信上传视频(FPGA驱动).zip (480个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
ov5640_udp_pc.bit 3.86MB
ov5640_udp_pc_routed.dcp 1.29MB
ov5640_udp_pc_placed.dcp 1.09MB
ov5640_udp_pc_opt.dcp 856KB
ov5640_udp_pc.dcp 375KB
async_fifo_1024x32b.dcp 136KB
async_fifo_1024x32b.dcp 132KB
async_fifo_1024x32b.dcp 132KB
async_fifo_1024x32b.dcp 132KB
clk_wiz_0.dcp 11KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
compile.do 1KB
compile.do 1KB
compile.do 989B
compile.do 975B
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compile.do 737B
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compile.do 686B
simulate.do 362B
simulate.do 362B
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simulate.do 294B
simulate.do 294B
elaborate.do 229B
simulate.do 215B
simulate.do 195B
simulate.do 187B
elaborate.do 183B
elaborate.do 175B
wave.do 32B
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simulate.do 11B
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run.f 835B
run.f 807B
run.f 550B
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run.f 456B
usage_statistics_webtalk.html 52KB
xsim.ini 22KB
xsim.ini 22KB
xsim.ini 22KB
vivado.jou 794B
vivado.jou 789B
vivado.jou 780B
vivado.jou 733B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 104KB
runme.log 55KB
runme.log 52KB
runme.log 23KB
ov5640_udp_pc.lpr 343B
elab.opt 234B
elab.opt 188B
elab.opt 180B
vivado.pb 175KB
vivado.pb 87KB
vivado.pb 37KB
place_design.pb 30KB
route_design.pb 17KB
write_bitstream.pb 16KB
opt_design.pb 14KB
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