© 2018 Cadence Design Systems, Inc. All rights reserved. Do not distribute. Shared under NDA.
Cadence Palladium Z1
2 © 2018 Cadence Design Systems, Inc. All rights reserved. Do not distribute. Shared under NDA.
There is no “One Size Fits All”
Verification and software platforms need to interoperate
SDK OS
Simulation
•Highest speed
•Earliest in the
flow
•Ignore
hardware
Virtual
Platform
•Almost at speed
•Less accurate
(or slower)
•Before RTL
•Great to debug
(but less detail)
•Easy replication
Formal
Analysis
•Non-scalable
•Exhaustive
•Early RTL
•Great for IP
•No SW
execution
HDL
Simulation
•KHz range
•Accurate
•Excellent HW
debug
•Broadly
available
• Mixed-
abstractions
•Limited SW
execution
Acceleration
Emulation
•MHz Range
•RTL accurate
•After RTL is
available
•Good to debug
with full detail
•Expensive to
replicate
FPGA
Prototype
•10’s of MHz
•RTL accurate
•After stable
RTL is available
•OK to debug
•More expensive
than software to
replicate
Prototyping
Board
•Real time speed
•Fully accurate
•Post Silicon
•Difficult to debug
•Sometimes hard
to replicate
3 © 2018 Cadence Design Systems, Inc. All rights reserved. Do not distribute. Shared under NDA.
VIP
VERIFICATION IP
Perspec
™
SW-DRIVEN TEST
vManager
™
METRICS
Indago
™
DEBUG
Uniform multi-engine verification
Verification Fabric
Palladium
®
Z1
EMULATION
Xcelium
™
SIMULATION
JasperGold
®
FORMAL & STATIC
Protium
™
X1
FPGA PROTOTYPE
Cadence Verification Suite
Palladium differentiations
• Best-in-class engines
• Flow-driven engine
integrations
• Differentiated and
comprehensive solutions
Xcelium/Palladium
• Industry only hot-swap capability
• Simulation/emulation congruence
• Coverage merge capability
Palladium/Protium
• Common front-end flow
• Common SpeedBridge portfolio
• Emulation/prototype congruence
Benefits of processor-based emulation
• Predictability: compile and RT speed
• Verification productivity: fast bring-up & ToT
(e.g. best visibility/debug, advanced allocation, etc.)
• Versatility: solutions supporting over 20+ different use
models
4 © 2018 Cadence Design Systems, Inc. All rights reserved. Do not distribute. Shared under NDA.
Innovation and leadership in acceleration & emulation
Mercury
3.5 Mgates
550 KHz
CoBALT
Plus
14 Mgates
200 KHz
Palladium
128 Mgates
500 KHz
System
Realizer
3 Mgates
450 KHz
RPM
50K Gates
100Khz
Enterprise
MARS
1M Gates
200Khz
CoBALT
8 Mgates
100 KHz
CoBALT Ultra
128 Mgates
400 KHz
Mercury
Plus
10 Mgates
750 KHz
Palladium II
256 Mgates
750KHz
1987 to 2009
1995 to 2009
Palladium III
256 Mgates
1 MHz
Xtreme III
72 Mgates
600 KHz
Xtreme Server
36 Mgates
300 KHz
FPGA-based Architecture
Processor-based Architecture
Palladium XP
2048 Mgates
1.2MHz
Palladium XP II
2304 Mgates
1.4MHz
2010 2013
Verification
Computing
Platforms
2000
Quickturn
2005
Verisity/Axis
Next Generation
Data Center Ready
Emulation
2015 2020
Enterprise-class
VCP
5 © 2018 Cadence Design Systems, Inc. All rights reserved. Do not distribute. Shared under NDA.
Palladium Z1: XL configuration
Palladium Z1
Model S12A
24"
(0.61m)
38"
(0.97m)
84"
(2.13m)
Cooling
LTA
Cluster Control Drawer
Logic Cluster
Power Tray
Cluster Control Drawer
Logic Cluster
Power Tray
System Control Drawer
Power Tray
Target Connections
Logic board
Domain
Logic cluster
An offline cluster can be
serviced without affecting the
operations of online clusters
HW Attributes
Capacity
MGates
Memory
GBytes
Domain 4 8
Logic Board 32 64
Cluster 192 384
Rack 384 768
4Mgates
8GB
User
Memory
+
8GBytes of user memory
for every 4MGates of
user logic