Copyright © 2002, 2003 ARM Limited. All rights reserved.
ARM DDI 0211C
ARM1136
™
Revision: r0p1
Technical Reference Manual
ii Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0211C
ARM1136
Technical Reference Manual
Copyright © 2002, 2003 ARM Limited. All rights reserved.
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Change history
Date Issue Change
December 2002 A First Release for r0p0
February 2003 B Internal release for r0p1
February 2003 C First release for r0p1
ARM DDI 0211C Copyright © 2002, 2003 ARM Limited. All rights reserved. iii
Contents
ARM1136 Technical Reference Manual
Preface
About this document ................................................................................... xxii
Feedback .................................................................................................. xxvii
Chapter 1 Introduction
1.1 About the ARM1136J-S and ARM1136JF-S processors ............................ 1-2
1.2 Components of the processor ..................................................................... 1-3
1.3 Power management .................................................................................. 1-23
1.4 Configurable options ................................................................................. 1-25
1.5 Pipeline stages .......................................................................................... 1-26
1.6 Typical pipeline operations ....................................................................... 1-28
1.7 ARM1136JF-S architecture with Jazelle technology ................................. 1-34
1.8 ARM1136JF-S instruction set summary .................................................... 1-36
1.9 Silicon revision information ....................................................................... 1-55
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Processor operating states ......................................................................... 2-3
2.3 Instruction length ......................................................................................... 2-4
2.4 Data types ................................................................................................... 2-5
2.5 Memory formats .......................................................................................... 2-6
2.6 Addresses in an ARM1136JF-S system ..................................................... 2-8
Contents
iv Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0211C
2.7 Operating modes ........................................................................................ 2-9
2.8 Registers .................................................................................................. 2-10
2.9 The program status registers .................................................................... 2-16
2.10 Exceptions ................................................................................................ 2-23
Chapter 3 Control Coprocessor CP15
3.1 About control coprocessor CP15 ................................................................ 3-2
3.2 Accessing CP15 registers .......................................................................... 3-3
3.3 Summary of control coprocessor CP15 registers ...................................... 3-5
3.4 CP15 registers arranged by function ......................................................... 3-9
3.5 CP15 registers mapping ........................................................................... 3-12
3.6 Cache configuration and control ............................................................... 3-15
3.7 Debug access to caches and TLB ............................................................ 3-34
3.8 DMA control .............................................................................................. 3-51
3.9 Memory management unit configuration and control ............................... 3-65
3.10 TCM configuration and control ................................................................. 3-83
3.11 System performance monitoring .............................................................. 3-87
3.12 Overall system configuration and control ................................................. 3-93
Chapter 4 Unaligned and Mixed-Endian Data Access Support
4.1 About unaligned and mixed-endian support ............................................... 4-2
4.2 Unaligned access support .......................................................................... 4-3
4.3 Unaligned data access specification .......................................................... 4-7
4.4 Operation of unaligned accesses ............................................................. 4-18
4.5 Mixed-endian access support ................................................................... 4-22
4.6 Instructions to reverse bytes in a general-purpose register ...................... 4-26
4.7 Instructions to change the CPSR E bit ..................................................... 4-27
Chapter 5 Program Flow Prediction
5.1 About program flow prediction .................................................................... 5-2
5.2 Branch prediction ........................................................................................ 5-4
5.3 Return stack ............................................................................................... 5-8
5.4 Instruction Memory Barrier (IMB) instruction ............................................. 5-9
5.5 ARM1020T or later IMB implementation .................................................. 5-10
Chapter 6 Memory Management Unit
6.1 About the MMU ........................................................................................... 6-2
6.2 TLB organization ........................................................................................ 6-4
6.3 Memory access sequence .......................................................................... 6-7
6.4 Enabling and disabling the MMU ................................................................ 6-9
6.5 Memory access control ............................................................................. 6-11
6.6 Memory region attributes .......................................................................... 6-14
6.7 Memory attributes and types .................................................................... 6-17
6.8 MMU aborts .............................................................................................. 6-27
6.9 MMU fault checking .................................................................................. 6-29
6.10 Fault status and address .......................................................................... 6-33
Contents
ARM DDI 0211C Copyright © 2002, 2003 ARM Limited. All rights reserved. v
6.11 Hardware page table translation ............................................................... 6-35
6.12 MMU descriptors ....................................................................................... 6-43
6.13 MMU software-accessible registers .......................................................... 6-55
6.14 MMU and Write Buffer ............................................................................... 6-59
Chapter 7 Level One Memory System
7.1 About the level one memory system ........................................................... 7-2
7.2 Cache organization ..................................................................................... 7-3
7.3 Tightly-coupled memory .............................................................................. 7-8
7.4 DMA .......................................................................................................... 7-11
7.5 TCM and cache interactions ..................................................................... 7-13
7.6 Cache debug ............................................................................................. 7-17
7.7 Write Buffer .............................................................................................. 7-18
Chapter 8 Level Two Interface
8.1 About the level two interface ....................................................................... 8-2
8.2 Synchronization primitives .......................................................................... 8-7
8.3 AHB-Lite control signals in the ARM1136JF-S processor ........................... 8-9
8.4 Instruction Fetch Interface AHB-Lite transfers .......................................... 8-20
8.5 Data Read Interface AHB-Lite transfers .................................................... 8-24
8.6 Data Write Interface AHB-Lite transfers .................................................... 8-49
8.7 DMA Interface AHB-Lite transfers ............................................................. 8-64
8.8 Peripheral Interface AHB-Lite transfers .................................................... 8-66
8.9 AHB-Lite .................................................................................................... 8-69
Chapter 9 Clocking and Resets
9.1 ARM1136JF-S clocking ............................................................................... 9-2
9.2 Reset ........................................................................................................... 9-7
9.3 Reset modes ............................................................................................... 9-8
Chapter 10 Power Control
10.1 About power control .................................................................................. 10-2
10.2 Power management .................................................................................. 10-3
Chapter 11 Coprocessor Interface
11.1 About the ARM1136JF-S coprocessor interface ....................................... 11-2
11.2 Coprocessor pipeline ................................................................................ 11-3
11.3 Token queue management ..................................................................... 11-12
11.4 Token queues ......................................................................................... 11-16
11.5 Data transfer ........................................................................................... 11-20
11.6 Operations .............................................................................................. 11-25
11.7 Multiple coprocessors ............................................................................. 11-28
Chapter 12 Vectored Interrupt Controller Port
12.1 About the PL192 Vectored Interrupt Controller ......................................... 12-2
12.2 About the ARM1136JF-S VIC port ............................................................ 12-3
