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TI cc254x user guide
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TI CC254x用户编程指南,为TI公司嵌入式bluetooth开发重要参考资料
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CC253x System-on-Chip Solution for 2.4-GHz
IEEE 802.15.4 and ZigBee
®
Applications
A
CC2540/41 System-on-Chip Solution for
2.4-GHz Bluetooth
®
low energy Applications
User's Guide
Literature Number: SWRU191C
April 2009– Revised January 2012
Contents
Preface ...................................................................................................................................... 15
1 Introduction ...................................................................................................................... 19
1.1 Overview .................................................................................................................... 20
1.1.1 CPU and Memory ................................................................................................ 23
1.1.2 Clocks and Power Management ................................................................................ 23
1.1.3 Peripherals ........................................................................................................ 23
1.1.4 Radio ............................................................................................................... 25
1.2 Applications ................................................................................................................ 25
2 8051 CPU .......................................................................................................................... 27
2.1 8051 CPU Introduction .................................................................................................... 28
2.2 Memory ..................................................................................................................... 28
2.2.1 Memory Map ...................................................................................................... 28
2.2.2 CPU Memory Space ............................................................................................. 30
2.2.3 Physical Memory ................................................................................................. 30
2.2.4 XDATA Memory Access ......................................................................................... 36
2.2.5 Memory Arbiter ................................................................................................... 36
2.3 CPU Registers ............................................................................................................. 37
2.3.1 Data Pointers ...................................................................................................... 37
2.3.2 Registers R0–R7 ................................................................................................. 38
2.3.3 Program Status Word ............................................................................................ 38
2.3.4 Accumulator ....................................................................................................... 39
2.3.5 B Register ......................................................................................................... 39
2.3.6 Stack Pointer ...................................................................................................... 39
2.4 Instruction Set Summary ................................................................................................. 39
2.5 Interrupts .................................................................................................................... 43
2.5.1 Interrupt Masking ................................................................................................. 43
2.5.2 Interrupt Processing .............................................................................................. 47
2.5.3 Interrupt Priority ................................................................................................... 49
3 Debug Interface ................................................................................................................. 53
3.1 Debug Mode ............................................................................................................... 54
3.2 Debug Communication ................................................................................................... 54
3.3 Debug Commands ........................................................................................................ 56
3.3.1 Debug Configuration ............................................................................................. 58
3.3.2 Debug Status ...................................................................................................... 58
3.3.3 Hardware Breakpoints ........................................................................................... 59
3.4 Flash Programming ....................................................................................................... 60
3.4.1 Lock Bits ........................................................................................................... 60
3.5 Debug Interface and Power Modes ..................................................................................... 60
3.6 Registers .................................................................................................................... 62
4 Power Management and Clocks .......................................................................................... 63
4.1 Power Management Introduction ........................................................................................ 64
4.1.1 Active and Idle Mode ............................................................................................. 65
4.1.2 PM1 ................................................................................................................ 65
4.1.3 PM2 ................................................................................................................ 65
3
SWRU191C–April 2009–Revised January 2012 Contents
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4.1.4 PM3 ................................................................................................................ 65
4.2 Power-Management Control ............................................................................................. 65
4.3 Power-Management Registers .......................................................................................... 66
4.4 Oscillators and Clocks .................................................................................................... 69
4.4.1 Oscillators ......................................................................................................... 69
4.4.2 System Clock ..................................................................................................... 69
4.4.3 32 kHz Oscillators ................................................................................................ 70
4.4.4 Oscillator and Clock Registers .................................................................................. 70
4.5 Timer Tick Generation .................................................................................................... 72
4.6 Data Retention ............................................................................................................. 72
5 Reset ............................................................................................................................... 73
5.1 Power-On Reset and Brownout Detector .............................................................................. 74
5.2 Clock-Loss Detector ....................................................................................................... 74
6 Flash Controller ................................................................................................................ 75
6.1 Flash Memory Organization .............................................................................................. 76
6.2 Flash Write ................................................................................................................. 76
6.2.1 Flash-Write Procedure ........................................................................................... 76
6.2.2 Writing Multiple Times to a Word ............................................................................... 77
6.2.3 DMA Flash Write ................................................................................................. 77
6.2.4 CPU Flash Write .................................................................................................. 78
6.3 Flash Page Erase ......................................................................................................... 78
6.3.1 Performing Flash Erase From Flash Memory ................................................................ 79
6.3.2 Different Flash Page Size on CC2533 ......................................................................... 79
6.4 Flash DMA Trigger ........................................................................................................ 79
6.5 Flash Controller Registers ................................................................................................ 79
7 I/O Ports ........................................................................................................................... 81
7.1 Unused I/O Pins ........................................................................................................... 82
7.2 Low I/O Supply Voltage ................................................................................................... 82
7.3 General-Purpose I/O ...................................................................................................... 82
7.4 General-Purpose I/O Interrupts .......................................................................................... 82
7.5 General-Purpose I/O DMA ............................................................................................... 83
7.6 Peripheral I/O .............................................................................................................. 83
7.6.1 Timer 1 ............................................................................................................. 84
7.6.2 Timer 3 ............................................................................................................. 84
7.6.3 Timer 4 ............................................................................................................. 84
7.6.4 USART 0 ........................................................................................................... 85
7.6.5 USART 1 ........................................................................................................... 85
7.6.6 ADC ................................................................................................................ 86
7.6.7 Operational Amplifier and Analog Comparator ............................................................... 86
7.7 Debug Interface ............................................................................................................ 86
7.8 32-kHz XOSC Input ....................................................................................................... 86
7.9 Radio Test Output Signals ............................................................................................... 86
7.10 Power-Down Signal MUX (PMUX) ...................................................................................... 86
7.11 I/O Registers ............................................................................................................... 87
8 DMA Controller ................................................................................................................. 95
8.1 DMA Operation ............................................................................................................ 96
8.2 DMA Configuration Parameters ......................................................................................... 98
8.2.1 Source Address ................................................................................................... 98
8.2.2 Destination Address .............................................................................................. 98
8.2.3 Transfer Count .................................................................................................... 98
8.2.4 VLEN Setting ...................................................................................................... 98
8.2.5 Trigger Event ...................................................................................................... 99
4
Contents SWRU191C–April 2009–Revised January 2012
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8.2.6 Source and Destination Increment ............................................................................. 99
8.2.7 DMA Transfer Mode .............................................................................................. 99
8.2.8 DMA Priority ..................................................................................................... 100
8.2.9 Byte or Word Transfers ........................................................................................ 100
8.2.10 Interrupt Mask .................................................................................................. 100
8.2.11 Mode 8 Setting ................................................................................................. 100
8.3 DMA Configuration Setup ............................................................................................... 100
8.4 Stopping DMA Transfers ................................................................................................ 101
8.5 DMA Interrupts ........................................................................................................... 101
8.6 DMA Configuration Data Structure .................................................................................... 101
8.7 DMA Memory Access ................................................................................................... 101
8.8 DMA Registers ........................................................................................................... 104
9 Timer 1 (16-Bit Timer) ....................................................................................................... 107
9.1 16-Bit Counter ............................................................................................................ 108
9.2 Timer 1 Operation ........................................................................................................ 108
9.3 Free-Running Mode ..................................................................................................... 108
9.4 Modulo Mode ............................................................................................................. 108
9.5 Up/Down Mode ........................................................................................................... 109
9.6 Channel-Mode Control .................................................................................................. 109
9.7 Input Capture Mode ..................................................................................................... 109
9.8 Output Compare Mode .................................................................................................. 110
9.9 IR Signal Generation and Learning .................................................................................... 115
9.9.1 Introduction ...................................................................................................... 115
9.9.2 Modulated Codes ............................................................................................... 115
9.9.3 Non-Modulated Codes ......................................................................................... 116
9.9.4 Learning .......................................................................................................... 117
9.9.5 Other Considerations ........................................................................................... 117
9.10 Timer 1 Interrupts ........................................................................................................ 117
9.11 Timer 1 DMA Triggers ................................................................................................... 117
9.12 Timer 1 Registers ........................................................................................................ 118
9.13 Accessing Timer 1 Registers as Array ................................................................................ 123
10 Timer 3 and Timer 4 (8-Bit Timers) ..................................................................................... 125
10.1 8-Bit Timer Counter ...................................................................................................... 126
10.2 Timer 3/Timer 4 Mode Control ......................................................................................... 126
10.2.1 Free-Running Mode ........................................................................................... 126
10.2.2 Down Mode ..................................................................................................... 126
10.2.3 Modulo Mode ................................................................................................... 126
10.2.4 Up/Down Mode ................................................................................................. 126
10.3 Channel Mode Control .................................................................................................. 126
10.4 Input Capture Mode ..................................................................................................... 127
10.5 Output Compare Mode .................................................................................................. 127
10.6 Timer 3 and Timer 4 Interrupts ......................................................................................... 127
10.7 Timer 3 and Timer 4 DMA Triggers ................................................................................... 128
10.8 Timer 3 and Timer 4 Registers ......................................................................................... 128
11 Sleep Timer ..................................................................................................................... 133
11.1 General .................................................................................................................... 134
11.2 Timer Compare ........................................................................................................... 134
11.3 Timer Capture ............................................................................................................ 134
11.4 Sleep Timer Registers ................................................................................................... 135
12 ADC ............................................................................................................................... 137
12.1 ADC Introduction ......................................................................................................... 138
12.2 ADC Operation ........................................................................................................... 138
5
SWRU191C–April 2009–Revised January 2012 Contents
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Copyright © 2009–2012, Texas Instruments Incorporated
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