松翰8位带AD功能SN8P2711A资源-CSDN文库

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1 1 1 PRODUCT OVERVIEW 1.1 FEATURES  Features Selection Table CHIP ROM RAM Stack Timer I/O ADC ADC Int. Ref. Green Mode PWM Wake-up Pin No. Package TC0 TC1 Buzzer SN8P2711A 1K 64 4 V V 12 5+1 V V 2 5 DIP14/SOP14/ SSOP16  Memory configuration  Two 8-bit Timer/Counter ROM size: 1K * 16 bits. One 8-bit timer with external event counter, RAM size: 64 * 8 bits. Buzzer0 and PWM0. (TC0). One 8-bit timer with external event counter,  4 levels stack buffer. Buzzer1 and PWM1. (TC1).  5 interrupt sources  5+1 channel 12-bit SAR ADC. 3 internal interrupts: TC0, TC1, ADC Five external ADC input 2 external interrupt: INT0, INT1 One internal battery measurement Internal AD reference voltage (VDD, 4V, 3V, 2V).  I/O pin configuration Bi-directional: P0, P4, P5.  On chip watchdog timer and clock source is Input only: P0.4. Internal low clock RC type (16KHz(3V), 32KHz(5V)) Pull-up resisters: P0, P4, P5. Wakeup: P0 level change.  4 system clocks ADC input pin: P4.0~P4.4. External high clock: RC type up to 10 MHz External Interrupt trigger edge: External high clock: Crystal type up to 16 MHz P0.0 controlled by PEDGE register. Internal high clock: 16MHz RC type P0.1 is falling edge trigger only. Internal low clock: RC type 16KHz(3V), 32KHz(5V)  3-Level LVD  4 operating modes Reset system and power monitor. Normal mode: Both high and low clock active Slow mode: Low clock only.  Powerful instructions Sleep mode: Both high and low clock stop Instruction‟s length is one word. Green mode: Periodical wakeup by TC0 timer Most of instructions are one cycle only. All ROM area JMP/CALL instruction.  Package (Chip form support) All ROM area lookup table function (MOVC). DIP 14 pin SOP 14 pin  Fcpu (Instruction cycle) SSOP 16 pin Fcpu = Fosc/1, Fosc/2, Fosc/4, Fosc/8, Fosc/16,

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SN8P2711A

5+1-ch 12-bit SAR ADC 8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 1 Version 1.3

SN8P2711A

USER’S MANUAL

Version 1.3

SN8P2711A

SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not

assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent

rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product

could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or

unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against

all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of

the part.

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SN8P2711A

5+1-ch 12-bit SAR ADC 8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 3 Version 1.3

Table of Content

AMENDENT HISTORY ................................................................................................................................ 2

PRODUCT OVERVIEW ........................................................................................................................... 6

1.1 FEATURES ........................................................................................................................................ 6

1.2 SYSTEM BLOCK DIAGRAM .......................................................................................................... 7

1.3 PIN ASSIGNMENT ........................................................................................................................... 8

1.4 PIN DESCRIPTIONS ......................................................................................................................... 9

1.5 PIN CIRCUIT DIAGRAMS ............................................................................................................... 9

CENTRAL PROCESSOR UNIT (CPU) .................................................................................................. 11

2.1 PROGRAM MEMORY (ROM) ....................................................................................................... 11

2.1.1 RESET VECTOR (0000H) ...................................................................................................... 12

2.1.2 INTERRUPT VECTOR (0008H) ............................................................................................. 13

2.1.3 LOOK-UP TABLE DESCRIPTION ........................................................................................ 15

2.1.4 JUMP TABLE DESCRIPTION ............................................................................................... 17

2.1.5 CHECKSUM CALCULATION............................................................................................... 19

2.2 DATA MEMORY (RAM) ................................................................................................................ 20

2.2.1 SYSTEM REGISTER .............................................................................................................. 20

2.2.1.1 SYSTEM REGISTER TABLE ............................................................................................ 20

2.2.1.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 20

2.2.1.3 BIT DEFINITION of SYSTEM REGISTER ....................................................................... 21

2.2.2 ACCUMULATOR ................................................................................................................... 22

2.2.3 PROGRAM FLAG ................................................................................................................... 23

2.2.4 PROGRAM COUNTER........................................................................................................... 24

2.2.5 Y, Z REGISTERS..................................................................................................................... 26

2.2.6 R REGISTER ........................................................................................................................... 26

2.3 ADDRESSING MODE .................................................................................................................... 27

2.3.1 IMMEDIATE ADDRESSING MODE .................................................................................... 27

2.3.2 DIRECTLY ADDRESSING MODE ....................................................................................... 27

2.3.3 INDIRECTLY ADDRESSING MODE ................................................................................... 27

2.4 STACK OPERATION ...................................................................................................................... 28

2.4.1 OVERVIEW ............................................................................................................................. 28

2.4.2 STACK REGISTERS ............................................................................................................... 28

2.4.3 STACK OPERATION EXAMPLE.......................................................................................... 29

2.5 CODE OPTION TABLE .................................................................................................................. 30

2.5.1 Fcpu code option ...................................................................................................................... 30

2.5.2 Reset_Pin code option .............................................................................................................. 30

2.5.3 Security code option ................................................................................................................. 30

2.5.4 Noise Filter code option ........................................................................................................... 30

RESET ...................................................................................................................................................... 31

3.1 OVERVIEW ..................................................................................................................................... 31

3.2 POWER ON RESET ......................................................................................................................... 32

3.3 WATCHDOG RESET ...................................................................................................................... 32

3.4 BROWN OUT RESET ..................................................................................................................... 32

3.5 THE SYSTEM OPERATING VOLTAGE ....................................................................................... 33

3.6 LOW VOLTAGE DETECTOR (LVD) ............................................................................................ 33

3.7 BROWN OUT RESET IMPROVEMENT ....................................................................................... 35

3.8 EXTERNAL RESET ........................................................................................................................ 36

3.9 EXTERNAL RESET CIRCUIT ....................................................................................................... 36

3.9.1 Simply RC Reset Circuit .......................................................................................................... 36

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5+1-ch 12-bit SAR ADC 8-Bit Micro-Controller

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3.9.2 Diode & RC Reset Circuit ........................................................................................................ 37

3.9.3 Zener Diode Reset Circuit ........................................................................................................ 37

3.9.4 Voltage Bias Reset Circuit ....................................................................................................... 38

3.9.5 External Reset IC ...................................................................................................................... 38

SYSTEM CLOCK .................................................................................................................................... 39

4.1 OVERVIEW ..................................................................................................................................... 39

4.2 FCPU (INSTRUCTION CYCLE) ...................................................................................................... 39

4.3 NOISE FILTER ................................................................................................................................ 39

4.4 SYSTEM HIGH-SPEED CLOCK .................................................................................................... 40

4.4.1 HIGH_CLK CODE OPTION ................................................................................................... 40

4.4.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC) ............................................. 40

4.4.3 EXTERNAL HIGH-SPEED OSCILLATOR ........................................................................... 40

4.4.4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT ....................................................... 40

4.5 SYSTEM LOW-SPEED CLOCK ..................................................................................................... 41

4.6 OSCM REGISTER ........................................................................................................................... 42

4.7 SYSTEM CLOCK MEASUREMENT ............................................................................................. 42

4.8 SYSTEM CLOCK TIMING ............................................................................................................. 43

SYSTEM OPERATION MODE .............................................................................................................. 46

5.1 OVERVIEW ..................................................................................................................................... 46

5.2 NORMAL MODE ............................................................................................................................ 47

5.3 SLOW MODE .................................................................................................................................. 47

5.4 POWER DOWN MODE .................................................................................................................. 47

5.5 GREEN MODE ................................................................................................................................ 48

5.6 OPERATING MODE CONTROL MACRO .................................................................................... 49

5.7 WAKEUP ......................................................................................................................................... 50

5.7.1 OVERVIEW ............................................................................................................................. 50

5.7.2 WAKEUP TIME ...................................................................................................................... 50

INTERRUPT ............................................................................................................................................ 51

6.1 OVERVIEW ..................................................................................................................................... 51

6.2 INTEN INTERRUPT ENABLE REGISTER ................................................................................... 52

6.3 INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 53

6.4 GIE GLOBAL INTERRUPT OPERATION .................................................................................... 54

6.5 PUSH, POP ROUTINE..................................................................................................................... 55

6.6 EXTERNAL INTERRUPT OPERATION (INT0) ........................................................................... 56

6.7 INT1 (P0.1) INTERRUPT OPERATION ......................................................................................... 57

6.8 TC0 INTERRUPT OPERATION ..................................................................................................... 58

6.9 TC1 INTERRUPT OPERATION ..................................................................................................... 59

6.10 ADC INTERRUPT OPERATION ................................................................................................... 60

6.11 MULTI-INTERRUPT OPERATION ............................................................................................... 61

I/O PORT .................................................................................................................................................. 62

7.1 OVERVIEW ..................................................................................................................................... 62

7.2 I/O PORT MODE ............................................................................................................................. 63

7.3 I/O PULL UP REGISTER ................................................................................................................ 64

7.4 I/O PORT DATA REGISTER .......................................................................................................... 65

7.5 PORT 0/4 ADC SHARE PIN ............................................................................................................ 66

TIMERS.................................................................................................................................................... 69

8.1 WATCHDOG TIMER ...................................................................................................................... 69

8.2 TIMER/COUNTER 0 (TC0) ............................................................................................................ 71

8.2.1 OVERVIEW ............................................................................................................................. 71

8.2.2 TC0 TIMER OPERATION ...................................................................................................... 72

8.2.3 TC0M MODE REGISTER ....................................................................................................... 73

8.2.4 TC0X8, TC0GN FLAGS .......................................................................................................... 74

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8.2.5 TC0C COUNTING REGISTER .............................................................................................. 74

8.2.6 TC0R AUTO-LOAD REGISTER ............................................................................................ 75

8.2.7 TC0 EVENT COUNTER FUNCTION .................................................................................... 76

8.2.8 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)................................................................ 76

8.2.9 PULSE WIDTH MODULATION (PWM) .............................................................................. 77

8.2.10 TC0 TIMER OPERATION EXPLAME .................................................................................. 79

8.3 TIMER/COUNTER 1 (TC1) ............................................................................................................ 81

8.3.1 OVERVIEW ............................................................................................................................. 81

8.3.2 TC1 TIMER OPERATION ...................................................................................................... 82

8.3.3 TC1M MODE REGISTER ....................................................................................................... 83

8.3.4 TC1X8 FLAG ........................................................................................................................... 84

8.3.5 TC1C COUNTING REGISTER .............................................................................................. 84

8.3.6 TC1R AUTO-LOAD REGISTER ............................................................................................ 85

8.3.7 TC1 EVENT COUNTER FUNCTION .................................................................................... 86

8.3.8 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)................................................................ 86

8.3.9 PULSE WIDTH MODULATION (PWM) .............................................................................. 87

8.3.10 TC1 TIMER OPERATION EXPLAME .................................................................................. 89

5+1 CHANNEL ANALOG TO DIGITAL CONVERTER ..................................................................... 91

9.1 OVERVIEW ..................................................................................................................................... 91

9.2 ADC MODE REGISTER ................................................................................................................. 92

9.3 ADC DATA BUFFER REGISTERS ................................................................................................ 93

9.4 ADC REFERENCE VOLTAGE REGISTER................................................................................... 94

9.5 ADC OPERATION DESCRIPTION AND NOTIC ......................................................................... 94

9.5.1 ADC SIGNAL FORMAT ........................................................................................................ 94

9.5.2 ADC CONVERTING TIME .................................................................................................... 95

9.5.3 ADC PIN CONFIGURATION ................................................................................................ 96

9.6 ADC OPERATION EXAMLPE ....................................................................................................... 97

9.7 ADC APPLICATION CIRCUIT ........................................................................................................... 99

INSTRUCTION TABLE .................................................................................................................... 100

ELECTRICAL CHARACTERISTIC................................................................................................. 101

11.1 ABSOLUTE MAXIMUM RATING .............................................................................................. 101

11.2 ELECTRICAL CHARACTERISTIC ............................................................................................. 101

11.3 CHARACTERISTIC GRAPHS ..................................................................................................... 103

DEVELOPMENT TOOL ................................................................................................................... 104

12.1 SN8P2711 EV-KIT .......................................................................................................................... 104

12.2 ICE AND EV-KIT APPLICATION NOTIC .................................................................................... 106

OTP PROGRAMMING PIN .............................................................................................................. 107

13.1 WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT ............................................... 107

13.2 PROGRAMMING PIN MAPPING: ............................................................................................... 108

MARKING DEFINITION ................................................................................................................. 109

14.1 INTRODUCTION .......................................................................................................................... 109

14.2 MARKING INDETIFICATION SYSTEM .................................................................................... 109

14.3 MARKING EXAMPLE ................................................................................................................. 109

14.4 DATECODE SYSTEM .................................................................................................................. 110

PACKAGE INFORMATION ............................................................................................................ 111

15.1 P-DIP 14 PIN .................................................................................................................................. 111

15.2 SOP 14 PIN ..................................................................................................................................... 112

15.3 SSOP 16 PIN ................................................................................................................................... 113

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