没有合适的资源?快使用搜索试试~ 我知道了~
Channel Link I Design Guide
2星 需积分: 10 14 下载量 87 浏览量
2018-09-14
10:21:22
上传
评论 1
收藏 2.96MB PDF 举报
温馨提示
试读
22页
National Semiconductor,Channel Link Design Guide。 NI的channellink指南,方便理解接口规则
资源推荐
资源详情
资源评论
DS90CR215,DS90CR216A,DS90CR217,
DS90CR218A,DS90CR285,DS90CR286A,
DS90CR287,DS90CR288A,DS90CR481,
DS90CR482,DS90CR483A,DS90CR484A,
DS90CR485,DS90CR486
Literature Number: SNLA167
June 2006
National Semiconductor
Channel Link Design Guide
Introduction
Page 2
Design Guidelines
Pages 4 - 10
Cables & Connectors
Page 6
Chip Operation
Pages 12 - 15
Evaluation Kits
Pages 11
Speed vs Cable Length
Pages 18 - 19
2
Channel Link LVDS SerDes
“Virtual Ribbon Cable”
Introduction
National Semiconductor’s DS90CR2xx and DS90CR4xx
Channel Link serializers/deserializers (SerDes) are
among the easiest to use SerDes in the market. Unlike
most SerDes, Channel Link serialize wide buses, require
no synchronization training characters or patterns, re-
quire no clock source at the receiver end. Channel Link
SerDes have the lowest cost per gigabit and are among
the lowest power SerDes chipsets in the industry.
#HANNEL
,INK
3ER$ES
DATAADDRCTRLDATAADDRCTRL
34/0
/THER
3ER$ES
-UX
,644, ,6$3
$3#2
-UX
)NPUT,ATCH
-UX
0,,
Channel Link Operation
Channel Link SerDes are normally used as “virtual
ribbon cable” to serialize wide “data+address+control”
parallel buses such as PCI, UTOPIA, processor buses,
and control buses, etc. Instead of tackling the whole
bus with one multiplexer, the parallel clock SerDes
architecture employs a bank of 7-to-1 multiplexers, each
serializing its section of the bus separately. The result-
ing serial data streams travel to the receiver in parallel
with an additional clock signal pair that the receiver
uses to latch in and recover the data. This multi-channel
mux with parallel framing clock approach allows Chan-
nel Link to serialize very wide parallel buses up to 48
bits automatically without external system intervention
or alignment procedures.
Channel Link SerDes deliver benefits over non-serializa-
tion such as fewer wires (especially grounds), lower
power, longer cable driving capability, lower noise/EMI,
and lower cable/connector costs. Not being confined to
using one serial pair, Channel Link SerDes can be made
arbitrarily wide and also avoid the design issues associ-
ated with ultra high speed serial data rates. Channel
Link offers excellent price/performance and is often the
only practical way to transmit a traditional wide parallel
bus over several meters of cable. Channel Link SerDes
chipsets are available in 21-, 28-, and 48- bit parallel
bus widths.
3
Channel Link Products Selection Guide
Channel Link LVDS Serializers & Deserializers
Features
• Wide 21-, 28-, and 48- bit bus widths
• Raw data payloads up to 6.38 Gbps
• Automatic receiver lock without training patterns or
characters, “Plug & Go”
• No external coding or framing required
• Very low power consumption
• Wide operating frequency, relaxed transmit clock
requirements
• Deserializer requires no external clock source
• Lowest cost per gigabit
• Easy to use over cables
and FR-4 backplanes
• Extended temperature
ranges
• 3.3V and 5V chipset
interoperability
• Standard TSSOP &
TQFP packaging
Which 48-bit Chipset Should I Use?
Clock Frequency Recommended Chipset
< 66 MHz DS90CR483/484
66 - 112 MHz DS90CR481/482,
DS90CR481/486†, or
DS90CR485/6
> 112 MHz DS90CR485/486
† For long cables (e.g. over 8 m) at ≥ 66 MHz, the DS90CR481/486
combination is recommended.
Part Number Mux
Ratio
Function Bus Speed
(MHz)
Through-
put (Gbps)
Supply
Voltage
Temperature Package Eval Kit
21-bit
DS90CR213MTD 21:3 Transmitter 20 - 66 1.38 5 -10 to +70°C TSSOP-48 See Note 1
DS90CR214MTD 21:3 Receiver 20 - 66 1.38 5 -10 to +70°C TSSOP-48 See Note 1
DS90CR215MTD 21:3 Transmitter 20 - 66 1.38 3.3 -40 to +85°C TSSOP-48 See Note 1
DS90CR216AMTD 21:3 Receiver 20 - 66 1.38 3.3 -40 to +85°C TSSOP-48 See Note 1
DS90CR217MTD 21:3 Transmitter 20 - 85 1.78 3.3 -10 to +70°C TSSOP-48 See Note 1
DS90CR218AMTD 21:3 Receiver 20 - 85 1.78 3.3 -10 to +70°C TSSOP-48 See Note 1
28-bit
DS90CR283MTD 28:4 Transmitter 20 - 66 1.84 5 -10 to +70°C TSSOP-56 See Note 1
DS90CR284MTD 28:4 Receiver 20 - 66 1.84 5 -10 to +70°C TSSOP-56 See Note 1
DS90CR285MTD 28:4 Transmitter 20 - 66 1.84 3.3 -40 to +85°C TSSOP-56 See Note 1
DS90CR286AMTD 28:4 Receiver 20 - 66 1.84 3.3 -40 to +85°C TSSOP-56 See Note 1
DS90CR287MTD 28:4 Transmitter 20 - 85 2.38 3.3 -10 to +70°C TSSOP-56 CLINK3V28BT-85
DS90CR288AMTD 28:4 Receiver 20 - 85 2.38 3.3 -10 to +70°C TSSOP-56 CLINK3V28BT-85
48-bit
DS90CR481VJD 48:8 Transmitter 65 - 112 5.37 3.3 -10 to +70°C TQFP-100 CLINK3V48BT-112
DS90CR482VS
2
48:8 Receiver 65 - 112 5.37 3.3 -10 to +70°C TQFP-100 CLINK3V48BT-112
DS90CR483VJD 48:8 Transmitter 33 - 112 5.37 3.3 -10 to +70°C TQFP-100 CLINK3V48BT-112
DS90CR484VJD 48:8 Receiver 33 - 112 5.37 3.3 -10 to +70°C TQFP-100 CLINK3V48BT-112
DS90CR485VS
2
48:8 Transmitter 66 - 133 6.38 2.5/3.3 -10 to +70°C TQFP-100 CLINK3V48BT-133
DS90CR486VS
2
48:8 Receiver 66 - 133 6.38 3.3 -10 to +70°C TQFP-100 CLINK3V48BT-133
1
Use 85 MHz 28-bit evaluation kit for proof of concept. This evaluation kit can be reworked to accept non-85 MHz, non-28-bit devices if necessary.
2
Package codes: National has recently moved to 2-letter package code suffixes for new products. Therefore, the new VS code refers to the same TQFP-100 pack-
age as the old VJD code.
4
Design Guidelines
General Information
Bus Topologies
Channel Link SerDes chipsets are designed for use over point-to-point cable and FR-4 backplane applications. Although multidrop backplanes
have been implemented with Channel Link, multidrop operation is not recommended above 40 MHz.
Bus LVDS
Embedded Clock SerDes
Channel Link
Parallel Clock SerDes
Bit Interleave
SerDes
100
4:1
Quad 4:1
10:1
20 - 80 MHz
16:1
18:1
21:3
28:4
48:8
Hex 10:1
625 MHz
625 MHz
10:1
25 - 80 MHz
15 - 66 MHz
20 - 85 MHz
20 - 85 MHz
33 - 133 MHz
16 - 66 MHz
250 500 1000 1500
Data Payload (Mbps)
Mux Ratio
2500 5000 10000 20000
SCAN50C400
DS92LV1023/1224 & SCAN921025/1226
DS92LV16
DS92LV18
24:1
5 - 35 MHz
DS90C241/124
DS90CR21x
DS90CR28x
DS90CR48x
SCAN928028/6260 (6 Channels)
SCAN50C400 (4 Ch)
Channel Link SerDes
$3#2
#LOCK)N
BITS
$ATA)N
BITS
$ATA/UT
0RE%MPHASIS
0,,
)NPUT&)&/
0ARALLELTO3ERIAL
$3#2
#LOCK/UT
$ESKEW
0,,
/UTPUT&)&/
3ERIALTO0ARALLEL
Typical Channel Link point-to-point application
剩余21页未读,继续阅读
资源评论
- 希望缄默2020-11-21没什么用的
lovingcloud
- 粉丝: 0
- 资源: 4
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功