1
MX25L12845E
P/N: PM1428
REV. 0.06, MAR. 05, 2009
MX25L12845E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
PRELIMINARY
2
MX25L12845E
P/N: PM1428
REV. 0.06, MAR. 05, 2009
Contents
FEATURES .................................................................................................................................................................. 5
GENERAL DESCRIPTION ......................................................................................................................................... 7
Table 1. Additional Features .................................................................................................................................... 7
PIN CONFIGURATION ................................................................................................................................................ 8
PIN DESCRIPTION ...................................................................................................................................................... 8
BLOCK DIAGRAM ....................................................................................................................................................... 9
DATA PROTECTION .................................................................................................................................................. 10
Table 2. Protected Area Sizes ................................................................................................................................. 11
Table 3. 4K-bit Secured OTP Denition .................................................................................................................. 11
Memory Organization ............................................................................................................................................... 12
Table 4. Memory Organization ............................................................................................................................... 12
DEVICE OPERATION ................................................................................................................................................ 13
Figure 1-1. Serial Modes Supported (for Normal Serial mode) .............................................................................. 13
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode) ................................................ 13
COMMAND DESCRIPTION ....................................................................................................................................... 14
Table 7. Command Sets ......................................................................................................................................... 14
(1) Write Enable (WREN) ....................................................................................................................................... 16
(2) Write Disable (WRDI) ........................................................................................................................................ 16
(3) Read Identication (RDID) ................................................................................................................................ 16
(4) Read Status Register (RDSR) ........................................................................................................................... 17
(5) Write Status Register (WRSR) .......................................................................................................................... 18
Protection Modes .................................................................................................................................................... 18
(6) Read Data Bytes (READ) .................................................................................................................................. 19
(7) Read Data Bytes at Higher Speed (FAST_READ) ............................................................................................ 19
(8) 2 x I/O Read Mode (2READ) ............................................................................................................................. 19
(9) 4 x I/O Read Mode (4READ) ............................................................................................................................. 20
(10) Fast Double Transfer Rate Read (FASTDTRD) .............................................................................................. 20
(11) 2 x I/O Double Transfer Rate Mode (2DTRD) ................................................................................................. 20
(12) 4 x I/O Double Transfer Rate Mode (4DTRD) ................................................................................................. 21
(13) Sector Erase (SE) ........................................................................................................................................... 21
(14) Block Erase (BE) ............................................................................................................................................. 22
(15) Block Erase (BE32K) ....................................................................................................................................... 22
(16) Chip Erase (CE) .............................................................................................................................................. 22
Program/Erase Flow(1) with read array data .......................................................................................................... 24
Program/Erase Flow(2) without read array data ..................................................................................................... 25
(17) Page Program (PP) ......................................................................................................................................... 26
(18) 4 x I/O Page Program (4PP) ........................................................................................................................... 26
(19) Continuously program mode (CP mode) ......................................................................................................... 26
(20) Parallel Mode (Highly recommended for production throughputs increasing) ................................................. 27
(21) Deep Power-down (DP) .................................................................................................................................. 27
(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ................................................... 28
(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D) ............................. 28
Table 8. ID Denitions ............................................................................................................................................ 29
(24) Enter Secured OTP (ENSO) ........................................................................................................................... 29
(26) Read Security Register (RDSCUR) ................................................................................................................. 29
(25) Exit Secured OTP (EXSO) .............................................................................................................................. 30
Security Register Denition .................................................................................................................................... 30
(27) Write Security Register (WRSCUR) ................................................................................................................ 30
3
MX25L12845E
P/N: PM1428
REV. 0.06, MAR. 05, 2009
(28) Write Protection Selection (WPSEL) ............................................................................................................... 31
WPSEL Flow ........................................................................................................................................................... 31
(29) Single Block Lock/Unlock Protection (SBLK/SBULK) ..................................................................................... 32
Block Lock Flow ...................................................................................................................................................... 32
Block Unlock Flow .................................................................................................................................................. 33
(30) Read Block Lock Status (RDBLOCK) ............................................................................................................. 34
(31) Gang Block Lock/Unlock (GBLK/GBULK) ....................................................................................................... 34
(32) Clear SR Fail Flags (CLSR) ............................................................................................................................ 35
(33) Enable SO to Output RY/BY# (ESRY) ............................................................................................................ 35
(34) Disable SO to Output RY/BY# (DSRY) ........................................................................................................... 35
POWER-ON STATE ................................................................................................................................................... 36
ELECTRICAL SPECIFICATIONS .............................................................................................................................. 37
ABSOLUTE MAXIMUM RATINGS ......................................................................................................................... 37
Figure 2. Maximum Negative Overshoot Waveform ............................................................................................... 37
CAPACITANCE TA = 25°C, f = 1.0 MHz ................................................................................................................. 37
Figure 3. Maximum Positive Overshoot Waveform ................................................................................................. 37
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL .................................................................. 38
Figure 5. OUTPUT LOADING ................................................................................................................................ 38
Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ....... 39
Table 10. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ..... 40
Timing Analysis ........................................................................................................................................................ 42
Figure 6. Serial Input Timing ................................................................................................................................... 42
Figure 7. Output Timing .......................................................................................................................................... 42
Figure 8. Serial Input Timing for Double Transfer Rate Mode ................................................................................ 43
Figure 9. Serial Output Timing for Double Transfer Rate Mode .............................................................................. 43
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ..................................................... 44
Figure 11. Write Enable (WREN) Sequence (Command 06) .................................................................................. 44
Figure 12. Write Disable (WRDI) Sequence (Command 04) .................................................................................. 44
Figure 13. Read Identication (RDID) Sequence (Command 9F) .......................................................................... 45
Figure 14. Read Identication (RDID) Sequence (Parallel) .................................................................................... 45
Figure 15. Read Status Register (RDSR) Sequence (Command 05) ..................................................................... 46
Figure 16. Write Status Register (WRSR) Sequence (Command 01) ................................................................... 46
Figure 17. Read Data Bytes (READ) Sequence (Command 03) ........................................................................... 47
Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ....................................................... 47
Figure 19. Fast DT Read (FASTDTRD) Sequence (Command 0D) ....................................................................... 48
Figure 20. 2 x I/O Read Mode Sequence (Command BB) ..................................................................................... 48
Figure 21. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD) ............................................................... 49
Figure 22. 4 x I/O Read Mode Sequence (Command EB) ..................................................................................... 49
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED) .............................................................. 50
Figure 24. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) ................................................. 51
Figure 25. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED) ......................... 52
Figure 26. Page Program (PP) Sequence (Command 02) .................................................................................... 53
Figure 27. 4 x I/O Page Program (4PP) Sequence (Command 38) ...................................................................... 53
Figure 28. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) ....................... 54
Figure 29. Sector Erase (SE) Sequence (Command 20) ...................................................................................... 54
Figure 30. Block Erase (BE) Sequence (Command D8) ....................................................................................... 54
Figure 31. Chip Erase (CE) Sequence (Command 60 or C7) ............................................................................... 55
Figure 32. Deep Power-down (DP) Sequence (Command B9) ............................................................................. 55
Figure 33. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) .. 55
Figure 34. Release from Deep Power-down (RDP) Sequence (Command AB) .................................................... 56
Figure 35. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF) .... 56
Figure 36. READ ARRAY SEQUENCE (Parallel) .................................................................................................. 57
Figure 37. AUTO PAGE PROGRAM TIMING SEQUENCE (Parallel) ................................................................... 58
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MX25L12845E
P/N: PM1428
REV. 0.06, MAR. 05, 2009
Figure 38. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Parallel) ............. 59
Figure 39. Read Electronic Manufacturer & Device ID (REMS) Sequence (Parallel) ............................................ 60
Figure 40. Write Protection Selection (WPSEL) Sequence (Command 68) .......................................................... 61
Figure 41. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39) ........................... 61
Figure 42. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C) ....................................... 61
Figure 43. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) ............................................. 62
Figure 44. Power-up Timing .................................................................................................................................... 63
Table 11. Power-Up Timing and VWI Threshold ..................................................................................................... 63
INITIAL DELIVERY STATE ..................................................................................................................................... 63
RECOMMENDED OPERATING CONDITIONS ......................................................................................................... 64
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 65
LATCH-UP CHARACTERISTICS .............................................................................................................................. 65
ORDERING INFORMATION ...................................................................................................................................... 66
PART NAME DESCRIPTION ..................................................................................................................................... 67
PACKAGE INFORMATION ........................................................................................................................................ 68
REVISION HISTORY ................................................................................................................................................. 69
5
MX25L12845E
P/N: PM1428
REV. 0.06, MAR. 05, 2009
PRELIMINARY
128M-BIT [x 1/x 2/x 4] CMOS MXSMIO
TM
(SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O
mode) structure
• 4096 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 512 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 256 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read (Normal Serial Mode)
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 70MHz with 4 dummy cycles
- 4 I/O: 70MHz with 6 dummy cycles
- Fast read (Double Transfer Rate Mode)
- 1 I/O: 50MHz with 6 dummy cycles
- 2 I/O: 50MHz with 6 dummy cycles
- 4 I/O: 50MHz with 8 dummy cycles
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 90ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 80s(typ.) /chip
• Low Power Consumption
- Low active read current: 45mA(max.) at 104MHz, 40mA(max.) at 66MHz and 30mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 100uA (max.)
- Deep power down current: 40uA (max.)
• Typical 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
