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74HC273PDF文档

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1. General description

The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL).

The 74HC273; 74HCT273 has eight edge-triggered, D-type ﬂip-ﬂops with individual

D inputs and Q outputs. The common clock (pin CP) and master reset (pin MR) inputs

load and reset (clear) all ﬂip-ﬂops simultaneously. The state of each D input, one set-up

time before the LOW-to-HIGH clock transition, is transferred to the corresponding output

(Qn) of the ﬂip-ﬂop.

All outputs will be forced LOW independently of clock or data inputs by a LOW voltage

level on the MR input.

The device is useful for applications where the true output only is required and the clock

and master reset are common to all storage elements.

2. Features

■ Ideal buffer for MOS microprocessor or memory

■ Common clock and master reset

■ Eight positive edge-triggered D-type ﬂip-ﬂops

■ Complies with JEDEC standard no. 7A

■ ESD protection:

◆ HBM EIA/JESD22-A114-C exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V

■ Multiple package options

■ Speciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

3. Quick reference data

74HC273; 74HCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Rev. 03 — 24 January 2006 Product data sheet

Table 1: Quick reference data

GND = 0 V; T

amb

= 25

C; t

= t

= 6 ns.

Symbol Parameter Conditions Min Typ Max Unit

74HC273

PHL

PLH

propagation delay CP to Qn V

= 5 V; C

=15pF - 15 - ns

PHL

HIGH-to-LOW propagation

delay

MR to Qn

= 5 V; C

=15pF - 15 - ns

max

maximum input clock

frequency

= 5 V; C

= 15 pF - 66 - MHz

Product data sheet Rev. 03 — 24 January 2006 2 of 26

Philips Semiconductors

74HC273; 74HCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

[1] C

is used to determine the dynamic power dissipation (P

in µW).

= C

× V

× f

× N+∑(C

× V

× f

) where:

= input frequency in MHz;

= output frequency in MHz;

= output load capacitance in pF;

= supply voltage in V;

N = number of inputs switching;

∑(C

× V

× f

) = sum of outputs.

4. Ordering information

input capacitance - 3.5 - pF

power dissipation

capacitance

per ﬂip-ﬂop; V

= GND

to V

[1]

-20-pF

74HCT273

PHL

PLH

propagation delay CP to Qn V

= 5 V; C

=15pF - 15 - ns

PHL

HIGH-to-LOW propagation

delay

MR to Qn

= 5 V; C

=15pF - 20 - ns

max

maximum input clock

frequency

= 5 V; C

= 15 pF - 36 - MHz

input capacitance - 3.5 - pF

power dissipation

capacitance

per ﬂip-ﬂop; V

= GND

to (V

− 1.5 V)

[1]

-23-pF

Table 1: Quick reference data

…continued

GND = 0 V; T

amb

= 25

C; t

= t

= 6 ns.

Symbol Parameter Conditions Min Typ Max Unit

Table 2: Ordering information

Type number Package

Temperature range Name Description Version

74HC273

74HC273N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

74HC273D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74HC273DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads; body width

5.3 mm

SOT339-1

74HC273PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body

width 4.4 mm

SOT360-1

74HC273BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin

quad ﬂat package; no leads; 20 terminals;

body 2.5 × 4.5 × 0.85 mm

SOT764-1

74HCT273

74HCT273N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

74HCT273D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

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