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单片机实例 proteus 仿真 51 （968个子文件）

00-59 Count 784B

00-59 Count 555B

00-99 Count 794B

00-99 Count 593B

4BIT-COUNT 862B

4BIT-COUNT 644B

4x4keyboard 2KB

6-BIT-count 6KB

8x8 lcd 4KB

8x8 lcd 3KB

8x8 lcd 1KB

99table 2KB

99table 1KB

electronic organ.__i 46B

6-BIT-count.__i 41B

VOLTMETER.__i 39B

8x8 lcd.__i 37B

counter.__i 37B

8x8 lcd.__i 37B

display.__i 37B

8x8 lcd.__i 37B

AD0809.__i 36B

temper.__i 36B

lock.__i 34B

electronic organ._ia 43B

8x8 lcd._ia 34B

AD0809._ia 33B

STARTUP.A51 6KB

STARTUP.A51 5KB

AD0809 5KB

AD0809 2KB

ADC0809 Basic 1KB

electronic organ.asm 6KB

4x4keyboard.asm 4KB

display.asm 4KB

digital clock.asm 3KB

AD0809.ASM 3KB

ADC0809 Basic.asm 2KB

99table.asm 2KB

Text3.asm 1KB

8x8 lcd.asm 1KB

doorbell.asm 1KB

8x8 lcd.asm 992B

8x8 lcd.asm 976B

count-ontime.asm 939B

count-ontime.asm 852B

flashled2.asm 848B

flashled.ASM 790B

multifunction-KEY.asm 786B

count-ontime.asm 647B

key-press.asm 629B

di..di..asm 597B

4BIT-COUNT.asm 594B

flashled.asm 540B

number.asm 507B

00-99 Count.asm 500B

00-59 Count.asm 461B

flashled.asm 453B

IO.ASM 347B

state.asm 343B

warn.asm 332B

starled2.asm 287B

led2.asm 210B

state2.asm 200B

lock_Uv2.Bak 2KB

starled2_Uv2.Bak 2KB

number_Uv2.Bak 2KB

starled__Uv2.Bak 2KB

4x4keyboard_Uv2.Bak 2KB

multifunction-KEY_Uv2.Bak 2KB

00-99 Count_Uv2.Bak 2KB

00-59 Count_Uv2.Bak 2KB

共 968 条

ADC0808/ADC0809

8-Bit µP Compatible A/D Converters with 8-Channel

Multiplexer

General Description

The ADC0808, ADC0809 data acquisition component is a

monolithic CMOS device with an 8-bit analog-to-digital con-

verter, 8-channel multiplexer and microprocessor compatible

control logic. The 8-bit A/D converter uses successive ap-

proximation as the conversion technique. The converter fea-

tures a high impedance chopper stabilized comparator, a

256R voltage divider with analog switch tree and a succes-

sive approximation register. The 8-channel multiplexer can

directly access any of 8-single-ended analog signals.

The device eliminates the need for external zero and

full-scale adjustments. Easy interfacing to microprocessors

is provided by the latched and decoded multiplexer address

inputs and latched TTL TRI-STATE

outputs.

The design of the ADC0808, ADC0809 has been optimized

by incorporating the most desirable aspects of several A/D

conversion techniques. The ADC0808, ADC0809 offers high

speed, high accuracy, minimal temperature dependence, ex-

cellent long-term accuracy and repeatability, and consumes

minimal power. These features make this device ideally

suited to applications from process and machine control to

consumer and automotive applications. For 16-channel mul-

tiplexer with common output (sample/hold port) see

ADC0816 data sheet. (See AN-247 for more information.)

Features

n Easy interface to all microprocessors

n Operates ratiometrically or with 5 V

or analog span

adjusted voltage reference

n No zero or full-scale adjust required

n 8-channel multiplexer with address logic

n 0V to 5V input range with single 5V power supply

n Outputs meet TTL voltage level specifications

n Standard hermetic or molded 28-pin DIP package

n 28-pin molded chip carrier package

n ADC0808 equivalent to MM74C949

n ADC0809 equivalent to MM74C949-1

Key Specifications

n Resolution 8 Bits

n Total Unadjusted Error

⁄

LSB and

1 LSB

n Single Supply 5 V

n Low Power 15 mW

n Conversion Time 100 µs

Block Diagram

TRI-STATE

is a registered trademark of National Semiconductor Corp.

DS005672-1

See Ordering

Information

June 1999

ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer

Connection Diagrams

Ordering Information

TEMPERATURE RANGE −40˚C to +85˚C −55˚C to +125˚C

Error

⁄

LSB Unadjusted ADC0808CCN ADC0808CCV ADC0808CCJ ADC0808CJ

1 LSB Unadjusted ADC0809CCN ADC0809CCV

Package Outline N28A Molded DIP V28A Molded Chip Carrier J28A Ceramic DIP J28A Ceramic DIP

Dual-In-Line Package

DS005672-11

Order Number ADC0808CCN or ADC0809CCN

See NS Package J28A or N28A

Molded Chip Carrier Package

DS005672-12

Order Number ADC0808CCV or ADC0809CCV

See NS Package V28A

www.national.com 2

Absolute Maximum Ratings (Notes 2, 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

) (Note 3) 6.5V

Voltage at Any Pin −0.3V to (V

+0.3V)

Except Control Inputs

Voltage at Control Inputs −0.3V to +15V

(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)

Storage Temperature Range −65˚C to +150˚C

Package Dissipation at T

25˚C 875 mW

Lead Temp. (Soldering, 10 seconds)

Dual-In-Line Package (plastic) 260˚C

Dual-In-Line Package (ceramic) 300˚C

Molded Chip Carrier Package

Vapor Phase (60 seconds) 215˚C

Infrared (15 seconds) 220˚C

ESD Susceptibility (Note 8) 400V

Operating Conditions (Notes 1, 2)

Temperature Range (Note 1) T

MIN

≤T

MAX

ADC0808CCN,ADC0809CCN −40˚C≤T

≤+85˚C

ADC0808CCV, ADC0809CCV −40˚C ≤ T

≤ +85˚C

Range of V

(Note 1) 4.5 V

to 6.0 V

Electrical Characteristics

Converter Specifications: V

REF+

REF(−)

GND, T

MIN

≤T

MAX

and f

CLK

640 kHz unless otherwise stated.

Symbol Parameter Conditions Min Typ Max Units

ADC0808

Total Unadjusted Error 25˚C

⁄

LSB

(Note 5) T

MIN

to T

MAX

⁄

LSB

ADC0809

Total Unadjusted Error 0˚C to 70˚C

1 LSB

(Note 5) T

MIN

to T

MAX

⁄

LSB

Input Resistance From Ref(+) to Ref(−) 1.0 2.5 kΩ

Analog Input Voltage Range (Note 4) V(+) or V(−) GND−0.10 V

+0.10 V

REF(+)

Voltage, Top of Ladder Measured at Ref(+) V

+0.1 V

Voltage, Center of Ladder V

/2-0.1 V

/2 V

/2+0.1 V

REF(−)

Voltage, Bottom of Ladder Measured at Ref(−) −0.1 0 V

Comparator Input Current f

640 kHz, (Note 6) −2

0.5 2 µA

Electrical Characteristics

Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤V

≤5.25V,

−40˚C≤T

≤+85˚C unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

ANALOG MULTIPLEXER

OFF(+)

OFF Channel Leakage Current V

5V, V

5V,

25˚C 10 200 nA

MIN

to T

MAX

1.0 µA

OFF(−)

OFF Channel Leakage Current V

5V, V

25˚C −200 −10 nA

MIN

to T

MAX

−1.0 µA

CONTROL INPUTS

IN(1)

Logical “1” Input Voltage V

−1.5 V

IN(0)

Logical “0” Input Voltage 1.5 V

IN(1)

Logical “1” Input Current V

15V 1.0 µA

(The Control Inputs)

IN(0)

Logical “0” Input Current V

0 −1.0 µA

(The Control Inputs)

Supply Current f

CLK

640 kHz 0.3 3.0 mA

DATA OUTPUTS AND EOC (INTERRUPT)

OUT(1)

Logical “1” Output Voltage I

−360 µA V

−0.4 V

www.national.com3

Electrical Characteristics (Continued)

Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤V

≤5.25V,

−40˚C≤T

≤+85˚C unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

DATA OUTPUTS AND EOC (INTERRUPT)

OUT(0)

Logical “0” Output Voltage I

1.6 mA 0.45 V

OUT(0)

Logical “0” Output Voltage EOC I

1.2 mA 0.45 V

OUT

TRI-STATE Output Current V

5V 3 µA

0−3 µA

Electrical Characteristics

Timing Specifications V

REF(+)

5V, V

REF(−)

GND, t

20 ns and T

25˚C unless otherwise noted.

Symbol Parameter Conditions MIn Typ Max Units

Minimum Start Pulse Width (

Figure 5

) 100 200 ns

WALE

Minimum ALE Pulse Width (

Figure 5

) 100 200 ns

Minimum Address Set-Up Time (

Figure 5

)2550ns

Minimum Address Hold Time (

Figure 5

)2550ns

Analog MUX Delay Time R

0Ω (

Figure 5

) 1 2.5 µs

From ALE

OE Control to Q Logic State C

50 pF, R

10k (

Figure 8

) 125 250 ns

OE Control to Hi-Z C

10 pF, R

10k (

Figure 8

) 125 250 ns

Conversion Time f

640 kHz, (

Figure 5

) (Note 7) 90 100 116 µs

Clock Frequency 10 640 1280 kHz

EOC

EOC Delay Time (

Figure 5

) 0 8+2 µS Clock

Periods

Input Capacitance At Control Inputs 10 15 pF

OUT

TRI-STATE Output At TRI-STATE Outputs 10 15 pF

Capacitance

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless othewise specified.

Note 3: A zener diode exists, internally, from V

to GND and has a typical breakdown voltage of 7 V

Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater

than the V

n supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog V

does not exceed the supply voltage by more

than 100 mV, the output code will be correct. To achieve an absolute 0V

to 5V

input voltage range will therefore require a minimum supply voltage of 4.900 V

over temperature variations, initial tolerance and loading.

Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See

Figure 3

. None of these A/Ds requires a zero or full-scale adjust. How-

ever, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages

can be adjusted to achieve this. See

Figure 13

Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little

temperature dependence (

Figure 6

). See paragraph 4.0.

Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.

Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

www.national.com 4

Functional Description

Multiplexer. The device contains an 8-channel single-ended

analog signal multiplexer. A particular input channel is se-

lected by using the address decoder.

Table 1

shows the input

states for the address lines to select any channel. The ad-

dress is latched into the decoder on the low-to-high transition

of the address latch enable signal.

TABLE 1.

SELECTED ADDRESS LINE

ANALOG

CHANNEL

CBA

IN0 L L L

IN1 L L H

IN2 L H L

IN3 L H H

IN4 H L L

IN5 H L H

IN6 H H L

IN7 H H H

CONVERTER CHARACTERISTICS

The Converter

The heart of this single chip data acquisition system is its

8-bit analog-to-digital converter. The converter is designed to

give fast, accurate, and repeatable conversions over a wide

range of temperatures. The converter is partitioned into 3

major sections: the 256R ladder network, the successive ap-

proximation register, and the comparator. The converter’s

digital outputs are positive true.

The 256R ladder network approach (

Figure 1

) was chosen

over the conventional R/2R ladder because of its inherent

monotonicity, which guarantees no missing digital codes.

Monotonicity is particularly important in closed loop feedback

control systems. A non-monotonic relationship can cause os-

cillations that will be catastrophic for the system. Additionally,

the 256R network does not cause load variations on the ref-

erence voltage.

The bottom resistor and the top resistor of the ladder net-

work in

Figure 1

are not the same value as the remainder of

the network. The difference in these resistors causes the

output characteristic to be symmetrical with the zero and

full-scale points of the transfer curve. The first output transi-

tion occurs when the analog signal has reached +

⁄

LSB

and succeeding output transitions occur every 1 LSB later up

to full-scale.

The successive approximation register (SAR) performs 8 it-

erations to approximate the input voltage. For any SAR type

converter, n-iterations are required for an n-bit converter.

Figure 2

shows a typical example of a 3-bit converter. In the

ADC0808, ADC0809, the approximation technique is ex-

tended to 8 bits using the 256R network.

The A/D converter’s successive approximation register

(SAR) is reset on the positive edge of the start conversion

(SC) pulse. The conversion is begun on the falling edge of

the start conversion pulse. A conversion in process will be in-

terrupted by receipt of a new start conversion pulse. Con-

tinuous conversion may be accomplished by tying the

end-of-conversion (EOC) output to the SC input. If used in

this mode, an external start conversion pulse should be ap-

plied after power up. End-of-conversion will go low between

0 and 8 clock pulses after the rising edge of start conversion.

The most important section of the A/D converter is the com-

parator. It is this section which is responsible for the ultimate

accuracy of the entire converter. It is also the comparator

drift which has the greatest influence on the repeatability of

the device. A chopper-stabilized comparator provides the

most effective method of satisfying all the converter require-

ments.

The chopper-stabilized comparator converts the DC input

signal into an AC signal. This signal is then fed through a

high gain AC amplifier and has the DC level restored. This

technique limits the drift component of the amplifier since the

drift is a DC component which is not passed by the AC am-

plifier. This makes the entire A/D converter extremely insen-

sitive to temperature, long term drift and input offset errors.

Figure 4

shows a typical error curve for the ADC0808 as

measured using the procedures outlined in AN-179.

www.national.com5

评论收藏

内容反馈

zpqywzq6f

2013-01-20

值得新手学习，谢谢！
zhanzhanzhanzhan0000

2013-05-23

资源很丰富，不错~~
yuling0916

2013-03-22

非常好的学习资料，里面有Proteus的仿真，有C语言和汇编语言的程序，真心好
普通网友

2014-06-18

例子很多，非常有用。
kevin_2009

2012-12-15

可以学习，值得新手学习

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