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FT2232

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DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 1 of 51

FT2232L Dual USB UART / FIFO I.C.

The FT2232L is the lead free version of FTDI’s 3

generation USB UART / FIFO I.C. family. This device features two

Multi-Purpose UART / FIFO controllers which can be conﬁgured individually in several different modes. As well as a

UART interface, FIFO interface and Bit-Bang IO modes of the 2

generation FT232BM and FT245BM devices, the

FT2232L offers a variety of additional new modes of operation, including a Multi-Protocol Synchronous Serial Engine

interface which is designed speciﬁcally for synchronous serial protocols such as JTAG and SPI bus.

HARDWARE FEATURES

• Single Chip USB  Dual Channel Serial / Parallel

Ports with a variety of conﬁgurations

• Entire USB protocol handled on the chip...no USB-

speciﬁc ﬁrmware programming required

• FT232BM-style UART interface option with full

Handshaking & Modem interface signals

• UART Interface supports 7 / 8 bit data, 1 / 2 stop

bits, and Odd / Even / Mark / Space / No Parity

• Transfer Data Rate 300 to 1 Mega Baud (RS232)

• Transfer Data Rate 300 to 3 Mega Baud (TTL and

RS422 / RS485)

• Auto Transmit Enable control for RS485 serial

applications using TXDEN pin

• FT245BM-style FIFO interface option with bi-

directional data bus and simple 4 wire handshake

interface

• Transfer Data Rate up to 1 MegaByte / Second

• Enhanced Bit-Bang Mode interface option

• New Synchronous Bit-Bang Mode interface option

• New Multi-Protocol Synchronous Serial Engine

(MPSSE) interface option

• New MCU Host Bus Emulation Mode option

• New Fast Opto-Isolated Serial Interface Mode

option

• Interface mode and USB Description strings

conﬁgurable in external EEPROM

• EEPROM Conﬁgurable on board via USB

• Support for USB Suspend and Resume conditions

via PWREN#, and SI / WU pins

• Support for bus powered, self powered, and high-

power bus powered USB conﬁgurations

• Integrated Power-On-Reset circuit, with optional

Reset input and Reset Output pins

• 5V and 3.3V logic IO Interfacing with independent

level conversion on each channel

• Integrated 3.3V LDO Regulator for USB IO

• Integrated 6MHz – 48Mhz clock multiplier PLL

• USB Bulk or Isochronous data transfer modes

• 4.35V to 5.25V single supply operating voltage

range

• UHCI / OHCI / EHCI host controller compatible

• USB 2.0 Full Speed (12 Mbits / Second)

compatible

• Compact 48-LD Lead Free LQFP package

VIRTUAL COM PORT (VCP) DRIVERS for

• Windows 98 / 98 SE / 2000 / ME / XP

• Linux 2.40 and greater

• Windows CE

• MAC OS-8 and OS-9**

• MAC OS-X

D2XX (USB Direct Drivers + DLL S/W Interface)

• Windows 98 / 98 SE / 2000 / ME / XP

• Linux 2.4 and Greater

APPLICATION AREAS

• USB Dual Port RS232 Converters

• USB  Dual Port RS422 / RS485 Converters

• Upgrading Legacy Peripheral Designs to USB

• USB Instrumentation

• USB JTAG Programming

• USB to SPI Bus Interfaces

• USB Industrial Control

• Field Upgradable USB Products

• Galvanically Isolated Products with USB Interface

[ ** = In planning or under development ]

1.1 Features Summary

1.0 Introduction

DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 3 of 51

FT2232L Dual USB UART / FIFO I.C.

• Two Individually Conﬁgurable IO Channels

Each of the FT2232L’s Channels (A and B) can be

individually conﬁgured as a FT232BM-style UART

interface, or as a FT245BM-style FIFO interface. In

addition these channel can be conﬁgured in a number

of special IO modes.

• Integrated Power-On-Reset (POR) circuit

The device incorporates an internal POR function.

A RESET# pin is available to allow external logic to

reset the device where required, however for most

applications this pin can simply be hardwired to Vcc.

A RSTOUT# pin is provided in order to allow the new

POR circuit to provide a stable reset to external MCU

and other devices.

• Integrated RCCLK circuit

Used to ensure that the oscillator and clock multiplier

PLL frequency are stable prior to USB enumeration.

• Integrated level converter on UART / FIFO

interface and control signals

Each channel of the FT2232L has its own

independent VCCIO pin that can be supplied by

between 3V to 5V. This allows each channel’s output

voltage drive level to be individually conﬁgured. Thus

allowing, for example 3.3V logic to be interfaced

to the device without the need for external level

converter I.C.’s.

• Improved power management control for high-

power USB Bus Powered devices

The PWREN# pin will become active when the

device is enumerated by USB, and be deactivated

when the device is in USB suspend. This can be

used to directly drive a transistor or P-Channel

MOSFET in applications where power switching

of external circuitry is required. The BM pull down

enable feature (conﬁgured in the external EEPROM)

is also retained. This will make the device gently

pull down on the FIFO / UART IO lines when the

power is shut off (PWREN# is high). In this mode any

residual voltage on external circuitry is bled to GND

when power is removed, thus ensuring that external

circuitry controlled by PWREN# resets reliably when

power is restored.

• Support for Isochronous USB Transfers

Whilst USB Bulk transfer is usually the best choice

for data transfer, the scheduling time of the data is

not guaranteed. For applications where scheduling

latency takes priority over data integrity such as

transferring audio and low bandwidth video data,

the FT2232L offers the option of USB Isochronous

transfer via conﬁguration of bit in the EEPROM.

• Send Immediate / Wake Up Signal Pin on each

channel

There is a Send Immediate / Wake Up (SI/WU) signal

pins on each of the chips channels. These combine

two functions on one pin. If USB is in suspend mode

(and remote wakeup is enabled in the EEPROM),

strobing this pin low will cause the device to request

a resume from suspend (WakeUp) on the USB Bus.

Normally, this can be used to wake up the Host PC.

During normal operation, if this pin is strobed low

any data in the device RX buffer will be sent out over

USB on the next Bulk-IN request from the drivers

regardless of the packet size. This can be used to

optimise USB transfer speed for some applications.

• Low suspend current

The suspend current of the FT2232L is typically

under 100 μA (excluding the 1.5K pull up resistor on

USBDP) in USB suspend mode. This allows greater

margin for peripherals to meet the USB Suspend

current limit of 500uA.

The FT2232L incorporates all of the enhancements introduced for the second generation FT232BM and FT245BM

chips. These are summarised as follows :-

2.0 Features and Enhancements

DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 5 of 51

FT2232L Dual USB UART / FIFO I.C.

• Enhanced Asynchronous Bit-Bang Interface

The FT2232L supports FTDI’s BM chip Bit Bang

mode. In Bit Bang mode, the eight FIFO data lines

can be switched between FIFO interface mode

and an 8-bit Parallel IO port. Data packets can be

sent to the device and they will be sequentially sent

to the interface at a rate controlled by an internal

timer (equivalent to the baud rate prescaler). With

the FT2232L device this mode has been enhanced

so that the internal RD# and WR# strobes are now

brought out of the device which can be used to allow

external logic to be clocked by accesses to the Bit-

Bang IO bus.

• Synchronous Bit-Bang Interface

Synchronous Bit-Bang Mode differs from

Asynchronous Bit-Bang mode in that the device

is only read when it is written to. Thus making it

easier for the controlling program to measure the

response to an output stimulus as the data returned

is synchronous to the output data.

• High Output Drive Level Capabillity

The IO interface pins can be made to drive out at

three times the standard drive level thus allowing

multiple devices, or devices that require a greater

drive strength to be interfaced to the FT2232L. This

option is conﬁgured in the external EEPROM, ad can

be set individually for each channel.

• Multi-Protocol Synchronous Serial Engine

Interface (M.P.S.S.E.)

The Multi-Protocol Synchronous Serial Engine

(MPSSE) interface is a new option designed to

interface efﬁciently with synchronous serial protocols

such as JTAG and SPI Bus. It is very ﬂexible in that it

can be conﬁgured for different industry standards, or

proprietary bus protocols. For instance, it is possible

to connect one of the FT2232L’s channels to an

SRAM conﬁgurable FPGA as supplied by vendors

such as Altera and Xilinx. The FPGA device would

normally be un-conﬁgured (i.e. have no deﬁned

function) at power-up. Application software on the PC

could use the MPSSE to download conﬁguration data

to the FPGA over USB. This data would deﬁne the

hardware’s function on power up. The other FT2232

channel would be available for other devices.

This approach would allow a customer to create a

“generic” USB peripheral, who’s hardware function

can be deﬁned under control of the application

software. The FPGA based hardware could be easily

upgraded or totally changed simply by changing the

FPGA conﬁguration data ﬁle. (See FTDI’s MORPH-

IC development module for a practicle example,

www.morph-ic.com)

• MCU Host Bus Emulation

This new mode combines the ‘A’ and ‘B’ bus interface

to make the FT2232L interface emulate a standard

8048 / 8051 style MCU bus. This allows peripheral

devices for these MCU families to be directly

attached to the FT2232L with IO being performed

over USB with the help of MPSSE interface

technology.

• Fast Opto-Isolated Serial Interface

A new proprietary FTDI protocol is designed to

allow galvanically isolated devices to communicate

sychronously with the FT2232L using just 4 signal

wires (over two dual opto-isolators), and two power

lines. The peripheral circuitry controls the data

transfer rate in both directions, whilst maintaining

full data integrity. Maximum USB full speed data

rates can be acheived. Both ‘A’ and ‘B’ channels

can communicate over the same 4 wire interface if

desired.

In addition to the BM chip features, the FT2232L incorporates the following new features and interface modes :-

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zoujixing

2016-02-17

这个没什么用
zgsa521

2012-11-12

资料比较完整，还在研究中
yml1224

2013-04-17

是英文的，对我没有太大的帮助，现在在研究FT4232的USB转JTAG，没头绪
风之_镜花水月

2013-10-22

只是资料，不是想要的
qiuzhiqiuzhi1031

2013-11-20

是英文资料内容比较官方初学者理解起来有点困难

前往

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liyan0122

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