Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sat Mar 12 22:42:27 2022
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: sdram_rw_test_map.ncd
OUTPUT FILE: sdram_rw_test_pad.txt
PART TYPE: xc6slx9
SPEED GRADE: -3
PACKAGE: ftg256
Pinout by Pin Number:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 |sdram_data<2> |IOB |IO_L52N_M3A9_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE |
|A3 |sdram_data<0> |IOB |IO_L83N_VREF_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE |
|A4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A5 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | |
|A6 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | |
|A7 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | |
|A9 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | |
|A10 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | |
|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | |
|A12 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | |
|A14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | |
|A15 | | |TMS | | | | | | | | | | | |
|A16 | | |GND | | | | | | | | | | | |
|B1 |sdram_data<4> |IOB |IO_L50N_M3BA2_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE |
|B2 |sdram_data<3> |IOB |IO_L52P_M3A8_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE |
|B3 |sdram_data<1> |IOB |IO_L83P_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE |
|B4 | | |VCCO_0 | | |0 | | | | |any******| | | |
|B5 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | |
|B6 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | |
|B7 | | |GND | | | | | | | | | | | |
|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | |
|B9 | | |VCCO_0 | | |0 | | | | |any******| | | |
|B10 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | |
|B11 | | |GND | | | | | | | | | | | |
|B12 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | |
|B13 | | |VCCO_0 | | |0 | | | | |any******| | | |
|B14 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | |
|B15 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | |
|B16 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | |
|C1 |sdram_data<6> |IOB |IO_L50P_M3WE_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE |
|C2
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FPGA实现智能小车数字识别
共347个文件
bat:28个
tcl:26个
sh:25个
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FPGA实现智能小车数字识别 (347个子文件)
wrfifo.asy 985B
rdfifo.asy 985B
pll_clk.asy 821B
implement.bat 4KB
implement_synplify.bat 3KB
implement_synplify.bat 3KB
implement.bat 3KB
implement.bat 3KB
simulate_ncsim.bat 3KB
simulate_ncsim.bat 3KB
simulate_ncsim.bat 3KB
simulate_ncsim.bat 3KB
simulate_vcs.bat 3KB
simulate_vcs.bat 3KB
simulate_isim.bat 3KB
simulate_isim.bat 3KB
simulate_vcs.bat 3KB
simulate_vcs.bat 3KB
simulate_isim.bat 3KB
simulate_isim.bat 3KB
simulate_mti.bat 3KB
simulate_isim.bat 3KB
simulate_mti.bat 3KB
planAhead_ise.bat 3KB
planAhead_rdn.bat 3KB
planAhead_ise.bat 3KB
planAhead_ise.bat 3KB
simulate_mti.bat 2KB
simulate_mti.bat 2KB
simulate_mti.bat 2KB
simulate_mti.bat 2KB
sdram_rw_test.bgn 47KB
xr_fpga.bgn 9KB
xr_fpga.bit 333KB
sdram_rw_test.bit 333KB
sdram_rw_test_cs.blc 1KB
XR_FPGA_cs.blc 1022B
XR_FPGA.bld 9KB
sdram_rw_test.bld 3KB
ila0.cdc 17KB
ila.cdc 12KB
ila_pro_0.cdc 7KB
coregen.cgc 43KB
coregen.cgc 16KB
coregen.cgp 520B
coregen.cgp 520B
coregen.cgp 237B
XR_FPGA.cmd_log 7KB
sdram_rw_test.cmd_log 5KB
top_digital_recognition.cmd_log 1008B
sdram_rw_test.cpj 141KB
XR_FPGA_pad.csv 13KB
sdram_rw_test_pad.csv 13KB
wave_mti.do 4KB
wave_mti.do 4KB
wave_mti.do 4KB
wave_mti.do 4KB
simulate_mti.do 3KB
simulate_mti.do 3KB
simulate_mti.do 3KB
simulate_mti.do 3KB
wave.do 3KB
wave.do 3KB
simulate_mti.do 3KB
simulate_mti.do 3KB
sdram_rw_test.drc 40KB
xr_fpga.drc 2KB
AI_Car.gise 14KB
SDRAM_test.gise 14KB
rdfifo.gise 1KB
wrfifo.gise 1KB
pll_clk.gise 1KB
ila_pro_0.gise 1KB
icon_pro.gise 1KB
usage_statistics_webtalk.html 197KB
sdram_rw_test_summary.html 20KB
XR_FPGA_summary.html 19KB
XR_FPGA_envsettings.html 14KB
sdram_rw_test_envsettings.html 14KB
fifo_generator_v9_3_vinfo.html 10KB
fifo_generator_v9_3_vinfo.html 10KB
top_digital_recognition_envsettings.html 9KB
clk_wiz_v3_6_vinfo.html 7KB
top_digital_recognition_summary.html 6KB
par_usage_statistics.html 4KB
sdram_top_summary.html 4KB
ucli_commands.key 98B
ucli_commands.key 66B
ucli_commands.key 66B
ucli_commands.key 66B
ucli_commands.key 66B
ucli_commands.key 62B
coregen.log 2KB
coregen.log 2KB
coregen.log 2KB
webtalk.log 747B
rdfifo.lso 6B
wrfifo.lso 6B
XR_FPGA.lso 6B
sdram_rw_test.lso 6B
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