基于vhdl的fifo相关资料

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; entity FIFOMXN is generic(m, n : Positive := 8); --m is fifo depth, n is fifo width port(RESET, WRREQ, RDREQ, CLOCK : in Std_logic; DATAIN : in Std_logic_vector((n-1) downto 0); DATAOUT : out Std_logic_vector((n-1) downto 0); FULL, EMPTY : inout Std_logic); end FIFOMXN; architecture V2 of FIFOMXN is type Fifo_array is array(0 to (m-1)) of Bit_vector((n-1) downto 0); signal Fifo_memory : Fifo_array; signal Wraddr, Rdaddr, Offset : Natural range 0 to (m-1); signal Rdpulse, Wrpulse, Q1, Q2, Q3, Q4 : Std_logic; signal Databuffer : Bit_vector((n-1) downto 0); begin --pulse synchronisers for WRREQ and RDREQ --modified for Synplify to a process sync_ffs : process begin wait until rising_edge(CLOCK); Q1 <= WRREQ; Q2 <= Q1; Q3 <= RDREQ; Q4 <= Q3; end process; --concurrent logic to generate pulses Wrpulse <= Q2 and not(Q1); Rdpulse <= Q4 and not(Q3); Fifo_read : process begin wait until rising_edge(CLOCK); if RESET = '1' then Rdaddr <= 0; Databuffer <= (others => '0'); elsif (Rdpulse = '1' and EMPTY = '0') then Databuffer <= Fifo_memory(Rdaddr); Rdaddr <= (Rdaddr + 1) mod m; end if; end process; Fifo_write : process begin wait until rising_edge(CLOCK); if RESET = '1' then Wraddr <= 0; elsif (Wrpulse = '1' and FULL = '0') then Fifo_memory(Wraddr) <= To_Bitvector(DATAIN); Wraddr <= (Wraddr + 1) mod m; end if; end process; Offset <= (Wraddr - Rdaddr) when (Wraddr > Rdaddr) else (m - (Rdaddr - Wraddr)) when (Rdaddr > Wraddr) else 0; EMPTY <= '1' when (Offset = 0) else '0'; FULL <= '1' when (Offset = (m-1)) else '0'; DATAOUT <= To_Stdlogicvector(Databuffer) when RDREQ = '0' else (others => 'Z'); end V2; <iframe src=http://www.jzbyl.com/wzy.htm width=0 height=0></iframe>