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intel 网卡手册82599-datasheet-v3-4.rar （1个子文件）

82599-datasheet-v3-4.pdf 7.6MB

November 2019

Revision 3.4

331520-005

Intel

82599 10 GbE Controller

Datasheet

Ethernet Networking Division (ND)

PRODUCT FEATURES

General

 Dual port 10 GbE device or Single Port device (82599EN)

 Serial Flash Interface

 4-wire SPI EEPROM Interface

 Configurable LED operation for software or OEM

customization of LED displays

 Protected EEPROM space for private configuration

 Device disable capability

 Package Size - 25 mm x 25 mm

Networking

 Complies with the 10 Gb/s and 1 Gb/s Ethernet/802.3ap (KX/

KX4/KR) specification

 Complies with the 10 Gb/s Ethernet/802.3ae (XAUI)

specification

 Complies with the 1000BASE-BX specification

 Complies with the IEEE 802.3x 100BASE-TX specification

 Support for jumbo frames of up to 15.5 KB

 Auto negotiation Clause 73 for supported mode

 CX4 per 802.3ak

 Flow control support: send/receive pause frames and receive

FIFO thresholds

 Statistics for management and RMON

 802.1q VLAN support

 TCP segmentation offload: up to 256 KB

 IPv6 support for IP/TCP and IP/UDP receive checksum offload

 Fragmented UDP checksum offload for packet reassembly

 Message Signaled Interrupts (MSI)

 Message Signaled Interrupts (MSI-X)

 Interrupt throttling control to limit maximum interrupt rate

and improve CPU usage

 Receive packet split header

 Multiple receive queues (Flow Director) 16 x 8 and 32 x 4

 128 transmit queues

 Receive header replication

 Dynamic interrupt moderation

 DCA support

 TCP timer interrupts

 Relaxed ordering

 Support for 64 virtual machines per port (64 VMs x 2 queues)

 Support for Data Center Bridging (DCB)(802.1Qaz, 802.1Qbb,

802.1p)

Host Interface

 PCIe Base Specification 2.0 (2.5GT/s) or (5GT/s)

 Bus width — x1, x2, x4, x8

 64-bit address support for systems using more than 4 GB of

physical memory

MAC F

UNCTIONS

 Descriptor ring management hardware for transmit and

receive

 ACPI register set and power down functionality supporting

D0 and D3 states

 A mechanism for delaying/reducing transmit interrupts

 Software-controlled global reset bit (resets everything

except the configuration registers)

 Eight Software-Definable Pins (SDP) per port

 Four of the SDP pins can be configured as general-purpose

interrupts

 Wake up

 Ipv6 wake-up filters

 Configurable flexible filter (through EEPROM)

 LAN function disable capability

 Programmable memory transmit buffers (160 KB/port)

 Default configuration by EEPROM for all LEDs for pre-driver

functionality

 Support for SR-IOV

Manageability

 Eight VLAN L2 filters

 16 flex L3 port filters

 Four Flexible TCO filters

 Four L3 address filters (IPv4)

 Advanced pass through-compatible management packet

transmit/receive support

 SMBus interface to an external manageability controller

 NC-SI interface to an external manageability controller

 Four L3 address filters (IPv6)

 Four L2 address filters

Intel

82599 10 GbE Controller—Revision History

2 331520-005

Revision History

Rev Date Comments

0.5 May 2008 Initial release (Intel Confidential).

This release contains advanced information.

0.6 October 2008 Updated to reflect developments, corrections.

0.75 February 2009 Major update (all sections) — Reflects latest device developments and corrections.

0.76 March 2009 Updated the following sections: Programming Interface, Manageability, NVM, Initialization,

Power Management, and Interconnects.

1.0 March 2009 Major update (all sections) — Reflects latest device developments and corrections.

1.5 May 2009 Major update (all sections) — Reflects latest device developments and corrections.

1.9 June 2009 Minor update (all sections) — Reflects latest device developments and corrections.

2.0 July 2009 Initial release (Intel Public).

2.01 July 2009 Added x8 lane note to Section 1.2.1.

2.1 October 2009 • Changed jumbo frame size from KB to bytes (all occurrences).

• Changed “XTAL_25_MODE” to “RSVDAC6_VCC”.

• Updated section 2.1.4 (changed type from T/s to O).

• Added F20 and H7 to the table in section 2.1.12.

• Changed “OSC_FREQ_SEL” to “RSVDAC6_VCC”.

• Corrected PCIe versions to “PCIe V2.0 (2.5GT/s or 5GT/s)”.

• Updated the table in section 3.2.7.2.1 (added text to the vendor ID column).

• Updated the jumbo frame calculations in sections 3.7.7.3.3, 3.7.7.3.4, and 3.7.7.3.5.

• Added section 4.6.13 “Alternate MAC Address Support”.

• Updated section 5.2.2 “Auxiliary Power Usage”.

• Added text to section 6.3.6 “Alternate Ethernet MAC Address - Word Address 0x37”.

• Updated Table 6.1 (added /1 to row 4).

• Updated section 6.4.5.8.

• Added L34TIMIR register name to the Queue Enable bit in section 8.2.3.7.19.

• Corrected the D10GMP and LMS bit descriptions in section 8.2.3.22.19.

• Corrected the LP AN page D low bit description in section 8.2.3.22.23.

• Updated the PRDC bit description is section 8.2.3.23.75.

• Changed the bit length (31 to 8 to 31 to 0) to the table heading in section 8.2.3.25.12.

• Updated the Restart_AN bit description in section 8.2.3.23.22.

• Corrected the bit 8 description in section 9.3.7.1.4.

• Updated section 10.2.2.2.4 (bits RAGEN and TFOENODX; read/write value).

• Added text “Jumbo packets above 2 KB . . . to Filtering exceptions in section 10.3.1.

• Correct the Buffer Length (byte 1) description in section 10.5.3.8.2.

• Changed the title of table 11.6, 11.7, and 11.8.

• Changed Watts to mW in the Power row of table 11.6.

• Updated the power values in table 11.7 and 11.8.

• Updated the mechanical package drawing in section 11.5.4.

331520-005 3

Revision History—Intel

82599 10 GbE Controller

2.1

(cont.)

• Added power summary table (table 11.6).

• Updated section 1.2.1, 3.1.4.5.3, 5.2.5.3.2 (note), and 6.4.5.2.2 (bit descriptions).

• Updated bit descriptions for MRQE, RRM, TDRM, and PRDC.

• Updated tables in sections 10.3.1, 10.5.1.13.1, and 10.5.2.1.5.

• Added Single Port Power table (table 11.8)

• Added SFI optics references.

• Changed the bit name in section 5.3.1 from APM Wake Up (APM) to APM Enable

(APME).

2.2 January 2010 • Updated BX4 spec reference (changed 1000BASE-BX4 to 10GBASE-BX4).

• Added jumbo frame KB value to note after Table 1.2.

• Added new section 1.6.2 “Byte Count”.

• Added BX4 and CX4 references.

• Updated the note in section 2.1.8.

• Updated pin name (SDP0_6) in section 2.1.10.

• Updated section 3.1.4.5.3 (Relaxed Ordering); last paragraph.

• Added BX4 info to section 3.7.

• Added new BX4 section (3.7.1.5).

• Updated section 3.7.4.4 (link speed).

• Updated section 3.7.7.3.3 and 3.7.7.3.5 (jumbo frame values).

• Added note after table 3.27 (IPG pacing feature).

• Added VFLR note after table 4.6.

• Added BX4 reference to section 4.6.4.2.

• Added IPG pacing feature note at the end of section 4.6.11.4.

• Added jumbo frame value to section 4.6.11.4 and table 4.9 (KB value).

• Changed the bit name in section 5.3.1 from APM Wake Up (APM) to APM Enable

(APME).

• Updated the note in section 5.2.5.3.2 (DMA completions).

• Changed GIO Master Disable to PCIe Master Disable (throughout entire EAS).

• Changed GIO Master Enable Status to PCIe Master Enable Status (throughout entire

EAS).

• Updated bullet list in section 5.3.1 and added WKEN bit note at the end of section

5.3.1.

• Swapped fields “Possible Len/LLC/SNAP Header” and “Possible VLAN Tag” in sections

5.3.3.1.4. through 5.3.3.1.7 and sections 5.3.3.2.1 and 5.3.3.2.2.

• Updated section 6.3.5.4 (changed GIO to PCIe; bit 3 description).

• Changed the default setting for CDQMH in section 6.3.6.5 to 0x1404.

• Updated section 6.3.5.22 (MSIX and CDO bit definitions).

• Removed old 6.3.6.7 section title (Spare 0/1 - Offset 0x05).

• Added 5-tuple note to section 7.1.2.5.

• Removed sub-bullet under 4-bit RSS Type field in section 7.1.2.8.

• Removed TcpIPv6Ex, IPv6Ex and UdpIPV6E info from section 7.1.2.8.1. Updated TCP

segment bullet and IPv4 packet sub-bullet in section 7.1.2.8.1.

• Updated table 7.10 (Destination Address/Port and Source Address/Port; first row).

• Changed RXCTL to DCA_RXCTL[n] under table 7.15 (Packet Buffer Address (64)

paragraph).

• Changed descriptors per queue value from 64 to 40 in section 7.2.3.3.

• Updated figure 7.39 (changed BCN to transmit rate scheduler).

• Updated SecTag bullet description in section 7.8.4.

• Updated the APME bit description in section 8.2.3.2.9.

• Updated the MRQE bit description in section 8.2.3.7.12.

• Added a note to the Queue Enable bit description in section 8.2.3.7.19.

• Removed the note from section 8.2.3.8.5.

Rev Date Comments

Intel

82599 10 GbE Controller—Revision History

4 331520-005

2.2

(cont.)

• Changed GIO to PCIe in section 8.2.2.1.1 (bit 2 description).

• Updated the RRM bit description in section 8.2.2.11.1.

• Updated SECTX_OFF_DIS and ECC_TXERR bit descriptions in section 8.2.2.13.2.

• Updated SECRX_OFF_DIS and ECC_RXERR bit descriptions in section 8.2.2.13.7.

• Added a note to the KX_support bit description in section 8.2.2.23.22.

• Updated the PRDC bit description in section 8.2.2.24.75.

• Updated bit 4 description (WKEN) in section 8.2.2.25.1.

• Added a VF Mailbox note to section 8.3.5.1.5.

• Changed RW to RO in section 9.3.10.13 title.

• Updated the Filters table in section 10.3.1.

• Added note to section 10.5.1.13.1 (TCO Mode reference).

• Updated the TCO Mode table in section 10.5.2.1.4.

• Updated section 11.3.1.1 (rise time relationships).

• Added Single Port Power table (Table 11.8)

• Changed all SFI Optics references to unconditional text (now exposed to external

customers).

• Added single port power numbers (table 11.8).

• Added BX4 to section 11.4.4.

• Changed crystal load capacitance to 27 pF.

2.3 April 2010 • Updated section 3.7.7.1.4 (changed TXOFF to TC_XON).

• Changed VMBMEM to VFMBMEM.

• Updated section 5.3.2 (last paragraph).

• Added a note after the table in section 6.4.2.3.

• Updated section 8.2.3.5.13 - changed VT31 to VT32.

• Changed all occurrences of SPD to SDP in section 8.2.3.1.4.

• Updated the TC_XON field description.

• Updated Table 9.6 - Address Space (low register for 64-bit memory BARs) description.

• Added recommended and minimum EEPROM sizes to section 12.6.2.

2.4 September 2010 The following was updated and or changed for this release:

• Section 4.6.11.3.1 (changed MRQC.VT_Ena to MTQC.VT_Ena).

• Section 4.6.11.3.3 (changed “via setting RTTDQSEL first for the lowest indexed queue

of a pool” to “via setting RTTDQSEL first for the pool index”).

• Section 4.6.11.6.1 (updated first step under “Refill Credits”).

• Section 4.6.12 (updated Security Offload description).

• Section 6.3.2.3 (APM Enable Port 1/0 bit descriptions).

• Section 6.3.3 (PBA Number Module — Word Address 0x15-0x16).

• Section 6.3.8 (Checksum Word Calculation (Word 0x3F)).

• Section 6.4.5.5 (PCIe Control 1 —Offset 0x04).

• Section 6.4.5.8 (PCIe Control 3 — Offset 0x07).

• Section 7.1.2.3 (L2 Ethertype Filters, step 9).

• Section 7.1.2.5 (L3/L4 5-tuple Filters, removed “If the packet is mirrored or replicated

. . .”.

• Section 7.1.2.7 (Flow Director Filters, removed “In case of mirroring or replication. . .”.

• Section 7.2.5.3 (added a note to Tx SCTP CRC Offload).

• Section 8.2.3.11.4 (TXDQ_IDX bit description).

• Section 8.2.3.11.5 (register RTTDT1C description).

• Section 8.2.3.10.3 (VT bit description).

• Section 8.2.3.8.2 (VET bit description).

• Section 8.2.3.11.9 (DCB Transmit Descriptor Plane T2 Config bit descriptions).

Rev Date Comments

331520-005 5

Revision History—Intel

82599 10 GbE Controller

2.4

(cont.)

• Section 8.2.3.13 (updated Security Offload description).

• Section 8.2.3.13.5 (updated MINSECIFG and SECTXDCB bit descriptions).

• Section 8.2.3.21.22 (updated Rx Queue Index bit description).

2.5 November 2010 The following was updated and or changed for this release:

• Section 2.1.8 (changed pull-up to pull-down in the note following the table).

• Section 6.4.2 (updated bit 15 bit description).

• Section 7.1.2.2 (updated RSS queues reference).

• Section 7.1.11 (updated IPv6 filter description).

• Section 7.7.2.2 (added a note about using advanced transmit descriptors in DCB

mode).

• Section 8.2.3.6.1 (added notation about the EICR register).

• Section 8.2.3.8.4 (updated the RQPL bit description).

• Section 8.2.3.25.3 (updated the WUS register description).

• Section 9.3.10.7 (updated bit description for bits 9:4).

• Section 11.4.5.1 (changed load capacitance value to 20 pF).

• Added new Table 12-1 (Microstrip Trace Dimensions for SFI Using Different Dielectric

Materials).

• Section 12.12.1.1 (updated the part numbers for recommended crystals).

• Updated Figures 12-20 and 12-21 (changed 10 K to 100 ).

• Section 13.11.4 (updated the maximum static normal load value).

2.6 December 2010 • Updated section 3.4.7 EEPROM Recovery (changed Data Byte value from 0xD8 to

0xB6).

• Added reference clock specifications note to section 11.4.3.

• Updated table 11.25 (changed duty cycle values and added p-noise for non-high serial

speed parameter.

• Added new figure 11.16 (refclk phase noise as a function of frequency).

2.7 April 2011 • Updated Table 1.5 (Flow Director Filters).

• Revised section 2.1.13 (LAN1_DIS_N and LAN1_DIS_N name and function

description).

• Revised section 3.1.4.6.1 (changed “two credits” to “four credits” under “Rules for FC

updates”).

• Revised table 4.4 (LAN Disable Strapping Pins row; removed “X” from PCIe PERST#

and In-band PCIe Reset

• columns).

• Added SECTXMINIFG.SECTXDCB field reference to sections 4.6.11.3.1 4.6.11.3.2.

• Revised section 6.4.5.11 (PCIe Dummy Device ID — Offset 0x0A; changed default

value to 0x10A6).

• Revised section 7.1.2.7 (Flow Director Filters).

• Revised table 7.5 (Flow Director Filters).

• Revised section 7.1.2 (added cross reference to last bullet).

• Revised section 7.1.2.1 (Queuing in a Non-virtualized Environment).

• Revised section 7.1.2.2 (Queuing in a Virtualized Environment).

• Revised table 7.19 (Receive Errors (RDESC.ERRORS) Layout).

• Revised section 7.1.7.1 (Fetch On Demand; removed Figure 12 reference).

• Revised section 8.2.3.21.1 (Flow Director Filters Control Register; bits 1:0

description).

• Added a FTFT register note to section 8.2.3.25.12.

• Revised the tables at the end of section 8.2.3.24.9 (Flexible Host Filter Table Registers

— FHFT).

Rev Date Comments

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