用Verilog 写的时钟并用1602显示

State Machine - |lcd1602|next Name next.data7 next.data6 next.data5 next.data4 next.data3 next.data2 next.data1 next.data0 next.state11 next.state10 next.state9 next.state8 next.state7 next.state6 next.state5 next.state4 next.state3 next.state2 next.state1 next.state0 next.scan next.state0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 next.state1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 next.state2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 next.state3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 next.state4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 next.state5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 next.state6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 next.state7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 next.state8 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 next.state9 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 next.state10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 next.state11 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 next.data0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 next.data1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 next.data2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 next.data3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 next.data4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 next.data5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 next.data6 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 next.data7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 next.scan 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1