Validation of DDR2/3 Designs
30 May 2007
Page 5
Impact on Design and Validation
Clock Speeds reaching 1GHz
Parallel buses reaching the
speeds of serial technology
Tighter timing margins require
calibration and bus training for
DRAM, controller, and analyzer
capture
Crosstalk, impedance, EMI, and
jitter management
Noise susceptibility
Probe load effects are critical
100 MT/s
400 MT/s
800 MT/s
1.6 GT/s
3.2 GT/s
2000
2002
2005
2008+
2010+
Memory Speed
Roadmap
DDR4
DDR3
DDR2
DDR
SDR
Benefits of good signal integrity
Guarantees interoperability with
different vendors
Improved performance
More design margin
“I’m becoming a
microwave designer!”
