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AT89C51是一款经典的8位微控制器，由美国Atmel公司生产，现在已被Microchip Technology（微芯科技）收购。这款单片机在电子工程领域广泛应用，尤其是在嵌入式系统设计中，是初学者入门的理想选择。下面将详细阐述AT89C51的相关知识点。 1. **结构与特性** AT89C51采用CMOS工艺制造，内含4KB的EPROM（可擦写可编程只读存储器），可以存储程序代码。它有128字节的RAM（随机存取内存）用于数据处理，以及32个可编程I/O口线（P0、P1、P2、P3），这些端口可以作为输入或输出使用。此外，它还具备4个定时/计数器（Timer/Counter 0、1、2、3）和一个串行通信接口（UART）。 2. **指令系统** AT89C51使用MCS-51指令集，包含大约256条指令，包括数据处理、转移、控制等指令，支持16位算术运算和逻辑运算。这使得它能处理复杂的计算任务，并且具有较高的执行效率。 3. **定时器与中断** - **定时器/计数器**：定时器可以设置为工作在定时模式或计数模式，可以用于实现延时、频率测量等功能。每个定时器都可以在溢出时触发中断。 - **中断系统**：AT89C51有5个外部中断源和2个内部中断源，中断系统增强了系统的实时响应能力，使得程序可以根据外部事件灵活切换执行流程。 4. **串行通信** AT89C51内置的UART接口支持异步串行通信，通过RXD（接收）和TXD（发送）引脚与其他设备进行串行数据交换，常用于实现RS-232或SPI、I²C等通信协议。 5. **开发环境与编程** 对于AT89C51的学习，通常需要编程软件如Keil uVision或Proteus进行模拟仿真，以及编程器进行芯片烧录。编写好的C或汇编语言程序可以通过ISP（在系统编程）或DIP（在应用编程）方式写入到单片机的EPROM中。 6. **应用领域** AT89C51广泛应用于各种控制系统，如智能家居、工业自动化、汽车电子、仪器仪表、安防系统等。它的低功耗特性也使其在电池供电的便携式设备中得到应用。 7. **学习资源** "AT89C51.pdf"可能是该单片机的官方数据手册，包含了详细的电气特性、引脚描述、寄存器配置等信息。"说明.htm"可能是关于如何使用和编程的教程，而"avrw.com.txt"可能是某种编程工具的使用指南或者额外的参考资料。学习AT89C51，需要理解其硬件结构，掌握MCS-51指令集，熟悉中断和定时器的使用，以及串行通信的原理。通过实践项目，例如LED闪烁、温度监测、按键控制等，可以加深对单片机操作的理解。

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AT89C51.rar （3个子文件）

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(continued)

8-Bit

Microcontroller

with 4 Kbytes

Flash

Features

•

Compatible with MCS-51 Products

•

4 Kbytes of In-System Reprogrammable Flash Memory

Endurance: 1,000 Write/Erase Cycles

•

Fully Static Operation: 0 Hz to 24 MHz

•

Three-Level Program Memory Lock

•

128 x 8-Bit Internal RAM

•

32 Programmable I/O Lines

•

Two 16-Bit Timer/Counters

•

Six Interrupt Sources

•

Programmable Serial Channel

•

Low Power Idle and Power Down Modes

P1.0

P1.1

P0.0 (AD0)

P1.2

(INT0) P3.2

ALE/PROG

(RD) P3.7 P2.3 (A11)

(TXD) P3.1

EA/VPP

(WR) P3.6

P2.4 (A12)

(RXD) P3.0

P0.7 (AD7)

(T1) P3.5

P2.6 (A14)

RST

P0.6 (AD6)

P1.7

P0.5 (AD5)

P1.6

P0.4 (AD4)

P1.5

P0.3 (AD3)

P1.4

P0.2 (AD2)

P1.3

P0.1 (AD1)

(INT1) P3.3

PSEN

XTAL2 P2.2 (A10)

(T0) P3.4

P2.7 (A15)

XTAL1 P2.1 (A9)

GND P2.0 (A8)

P2.5 (A13)

Pin Configurations

PDIP/Cerdip

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4 Kbytes

of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufac-

tured using Atmel’s high density nonvolatile memory technology and is compatible with the

industry standard MCS-51 instruction set and pinout. The on-chip Flash allows the program

memory to be reprogrammed in-system or by a conventional nonvolatile memory program-

mer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51

is a powerful microcomputer which provides a highly flexible and cost effective solution to

many embedded control applications.

The AT89C51 provides the following standard features: 4 Kbytes of Flash, 128 bytes of

RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a

full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is

INDEX

CORNER

P1.0

VCC

P1.1

P1.2

P1.4

P1.3

P1.7

P1.6

P1.5

PSEN

XTAL1

GND

XTAL2

GND

P0.0 (AD0)

ALE/PROG

(RD) P3.7

EA/VPP

(WR) P3.6

(RXD) P3.0

P0.7 (AD7)

P2.6 (A14)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P0.2 (AD2)

P0.1 (AD1)

(INT0) P3.2

(TXD) P3.1

(T1) P3.5

(INT1) P3.3

(T0) P3.4

P2.7 (A15)

(A11) P2.3

(A12) P2.4

(A10) P2.2

(A9) P2.1

(A8) P2.0

RST

P2.5 (A13)

PQFP/TQFP

P1.0

VCC

P1.1

P0.0 (AD0)

P1.2

ALE/PROG

(RD) P3.7

XTAL1

EA/VPP

(WR) P3.6

GND

(RXD) P3.0

P0.7 (AD7)

P2.6 (A14)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P1.4

P0.2 (AD2)

P1.3

P0.1 (AD1)

PSEN

XTAL2

(INT0) P3.2

(TXD) P3.1

(T1) P3.5

(INT1) P3.3

(T0) P3.4

P2.7 (A15)

(A11) P2.3

(A12) P2.4

(A10) P2.2

(A9) P2.1

(A8) P2.0

RST

P1.7

P1.6

P1.5

INDEX

CORNER

P2.5 (A13)

444

20 24

17 29

PLCC/LCC

0265E

AT89C51

3-33

Block Diagram

3-34 AT89C51

Pin Description

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output

port each pin can sink eight TTL inputs. When 1s are written to

port 0 pins, the pins can be used as high-impedance inputs.

Port 0 may also be configured to be the multiplexed low-order

address/data bus during accesses to external program and data

memory. In this mode P0 has internal pullups.

Port 0 also receives the code bytes during Flash programming,

and outputs the code bytes during program verification. External

pullups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The

Port 1 output buffers can sink/source four TTL inputs. When 1s

are written to Port 1 pins they are pulled high by the internal

pullups and can be used as inputs. As inputs, Port 1 pins that are

externally being pulled low will source current (I

) because of

the internal pullups.

Port 1 also receives the low-order address bytes during Flash

programming and program verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The

Port 2 output buffers can sink/source four TTL inputs. When 1s

are written to Port 2 pins they are pulled high by the internal

pullups and can be used as inputs. As inputs, Port 2 pins that are

externally being pulled low will source current (I

) because of

the internal pullups.

Port 2 emits the high-order address byte during fetches from ex-

ternal program memory and during accesses to external data

memory that use 16-bit addresses (MOVX @ DPTR). In this

application it uses strong internal pullups when emitting 1s.

During accesses to external data memory that use 8-bit ad-

dresses (MOVX @ RI), Port 2 emits the contents of the P2 Spe-

cial Function Register.

Port 2 also receives the high-order address bits and some control

signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The

Port 3 output buffers can sink/source four TTL inputs. When 1s

are written to Port 3 pins they are pulled high by the internal

pullups and can be used as inputs. As inputs, Port 3 pins that are

externally being pulled low will source current (I

) because of

the pullups.

Port 3 also serves the functions of various special features of the

AT89C51 as listed below:

Port Pin

Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2

INT0 (extenal interrupt 0)

P3.3

INT1 (extenal interrupt 1)

P3.4 T0 (timer 0 extenal input)

P3.5 T1 (timer 1 external input)

P3.6

WR (extenal data memory write strobe)

P3.7

RD (external data memory read strobe)

Port 3 also receives some control signals for Flash programming

and programming verification.

RST

Reset input. A high on this pin for two machine cycles while the

oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of

the address during accesses to external memory. This pin is also

the program pulse input (

PROG) during Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6 the

oscillator frequency, and may be used for external timing or

clocking purposes. Note, however, that one ALE pulse is

skipped during each access to external Data Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR

location 8EH. With the bit set, ALE is active only during a

MOVX or MOVC instruction. Otherwise, the pin is weakly

pulled high. Setting the ALE-disable bit has no effect if the mi-

crocrontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program

memory.

When the AT89C51 is executing code from external program

memory,

PSEN is activated twice each machine cycle, except

that two

PSEN activations are skipped during each access to ex-

ternal data memory.

EA/V

External Access Enable. EA must be strapped to GND in order

to enable the device to fetch code from external program mem-

ory locations starting at 0000H up to FFFFH. Note, however,

that if lock bit 1 is programmed,

EA will be internally latched on

reset.

EA should be strapped to V

for internal program executions.

This pin also receives the 12-volt programming enable voltage

) during Flash programming, for parts that require 12-volt

(continued)

designed with static logic for operation down to zero frequency

and supports two software selectable power saving modes. The

Idle Mode stops the CPU while allowing the RAM, timer/count-

ers, serial port and interrupt system to continue functioning. The

Power Down Mode saves the RAM contents but freezes the os-

cillator disabling all other chip functions until the next hardware

reset.

Description (Continued)

AT89C51

3-35

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier which can be configured for use as an on-

chip oscillator, as shown in Figure 1. Either a quartz crystal or

ceramic resonator may be used. To drive the device from an ex-

ternal clock source, XTAL2 should be left unconnected while

XTAL1 is driven as shown in Figure 2. There are no require-

ments on the duty cycle of the external clock signal, since the

input to the internal clocking circuitry is through a divide-by-

two flip-flop, but minimum and maximum voltage high and low

time specifications must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip

peripherals remain active. The mode is invoked by software.

The content of the on-chip RAM and all the special functions

registers remain unchanged during this mode. The idle mode can

be terminated by any enabled interrupt or by a hardware reset.

It should be noted that when idle is terminated by a hardware

reset, the device normally resumes program execution, from

where it left off, up to two machine cycles before the internal

reset algorithm takes control. On-chip hardware inhibits access

to internal RAM in this event, but access to the port pins is not

inhibited. To eliminate the possibility of an unexpected write to

a port pin when Idle is terminated by reset, the instruction fol-

lowing the one that invokes Idle should not be one that writes to

a port pin or to external memory.

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

Figure 2. External Clock Drive Configuration

XTAL2

GND

XTAL1

Figure 1. Oscillator Connections

Notes: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF

± 10 pF for Ceramic Resonators

Status of External Pins During Idle and Power Down

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power Down Internal 0 0 Data Data Data Data

Power Down External 0 0 Float Data Data Data

XTAL1

Input to the inverting oscillator amplifier and input to the inter-

nal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Pin Description (Continued)

Power Down Mode

In the power down mode the oscillator is stopped, and the in-

struction that invokes power down is the last instruction exe-

cuted. The on-chip RAM and Special Function Registers retain

their values until the power down mode is terminated. The only

exit from power down is a hardware reset. Reset redefines the

SFRs but does not change the on-chip RAM. The reset should

not be activated before V

is restored to its normal operating

level and must be held active long enough to allow the oscillator

to restart and stabilize.

3-36 AT89C51

Program Memory Lock Bits

On the chip are three lock bits which can be left unprogrammed

(U) or can be programmed (P) to obtain the additional features

listed in the table below:

When lock bit 1 is programmed, the logic level at the

EA pin is

sampled and latched during reset. If the device is powered up

without a reset, the latch initializes to a random value, and holds

that value until reset is activated. It is necessary that the latched

value of

EA be in agreement with the current logic level at that

pin in order for the device to function properly.

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash mem-

ory array in the erased state (that is, contents = FFH) and ready

to be programmed. The programming interface accepts either a

high-voltage (12-volt) or a low-voltage (V

) program enable

signal. The low voltage programming mode provides a conven-

ient way to program the AT89C51 inside the user’s system,

while the high-voltage programming mode is compatible with

conventional third party Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or low-

voltage programming mode enabled. The respective top-side

marking and device signature codes are listed in the following

table.

= 12 V V

= 5 V

Top-Side Mark

AT89C51 AT89C51

xxxx xxxx-5

yyww yyww

Signature

(030H)=1EH (030H)=1EH

(031H)=51H (031H)=51H

(032H)=FFH (032H)=05H

The AT89C51 code memory array is programmed byte-by-byte

in either programming mode. To program any non-blank byte in

the on-chip Flash Memory, the entire memory must be erased

using the Chip Erase Mode.

Programming Algorithm: Before programming the AT89C51,

the address, data and control signals should be set up according

to the Flash programming mode table and Figures 3 and 4. To

program the AT89C51, take the following steps.

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise

EA/V

to 12 V for the high-voltage programming

mode.

5. Pulse ALE/

PROG once to program a byte in the Flash

array or the lock bits. The byte-write cycle is self-timed and

typically takes no more than 1.5 ms. Repeat steps 1

through 5, changing the address and data for the entire array

or until the end of the object file is reached.

Data Polling: The AT89C51 features Data Polling to indicate

the end of a write cycle. During a write cycle, an attempted read

of the last byte written will result in the complement of the writ-

ten datum on PO.7. Once the write cycle has been completed,

true data are valid on all outputs, and the next cycle may begin.

Data Polling may begin any time after a write cycle has been

initiated.

Ready/

Busy: The progress of byte programming can also be

monitored by the RDY/

BSY output signal. P3.4 is pulled low

after ALE goes high during programming to indicate BUSY.

P3.4 is pulled high again when programming is done to indicate

READY.

Program Verify: If lock bits LB1 and LB2 have not been pro-

grammed, the programmed code data can be read back via the

address and data lines for verification. The lock bits cannot be

verified directly. Verification of the lock bits is achieved by ob-

serving that their features are enabled.

Chip Erase: The entire Flash array is erased electrically by

using the proper combination of control signals and by holding

ALE/

PROG low for 10 ms. The code array is written with all

"1"s. The chip erase operation must be executed before the code

memory can be re-programmed.

Reading the Signature Bytes: The signature bytes are read by

the same procedure as a normal verification of locations 030H,

Lock Bit Protection Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features.

2PUU

MOVC instructions executed from external program memory are disabled from

fetching code bytes from internal memory,

is sampled and latched on reset, and

further programming of the Flash is disabled.

3 P P U Same as mode 2, also verify is disabled.

4 P P P Same as mode 3, also external execution is disabled.

AT89C51

3-37

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