HDLBits学习笔记.docx

HDLBits 学习笔记

一、

Implicit nets

Implicit nets are often a source of hard-to-detect bugs. In Verilog, net-type signals can

be implicitly created by anstatement or by attaching something undeclared

to a module port. Implicit nets are always one-bit wires and causes bugs if you had

intended to use a vector. Disabling creation of implicit nets can be done using

thedirective.

which makes the bug more visible.

Unpacked vs. Packed Arrays

You may have noticed that indeclarations, the vector indices are writtenbefore the

vector name. This declares the "packed" dimensions of the array, where the bits are

"packed" together into a blob (this is relevant in a simulator, but not in hardware).

Theunpackeddimensions are declaredafterthe name. They are generally used to

declare memory arrays. Since ECE253 didn't cover memory arrays, we have not used

packed arrays in this course.

Seehttp://www.asic-world.com/systemverilog/data_types10.htmlfor more details.

+$$,,,-.$***/%"

takes the entire 4-bit vectoraand assigns it to the entire 8-bit vectorw(declarations

are taken from above). If the lengths of the right and left sides don't match, it is zero-

extended or truncated as appropriate.

The part-select operator can be used to access a portion of a vector:

 1*2"

3#*"3

3##)))*"3

4%#%"4

" 5)6%$$***

)

Classical mistake:

module top_module(

input [7:0] in,

output [7:0] out

);

assign out[7:0]=in[0:7];

endmodule

vector bit ordering to be <ipped.

module top_module (

input [7:0] in,

output [31:0] out );

// assign out = { replicate-sign-bit , the-input };

Endmodule

$#-'#,:a#,:b:cin

#,:sum:cout:(

Use a 32-bit wide XOR gate to invert the"input whenever"is 1. (This can

also be viewed as" #XORed with sub replicated 32 times.

Seereplication operator.). Also connect the"input to the carry-in of the

减法器的门级电路思路

Anstatement usually creates a 2-to-1 multiplexer, selecting one input if







This is equivalent to using a continuousment with a conditional

'(:<3:

However, the proceduralstatement provides a new way to make mistakes.

The circuit is combinational only ifis always assigned a value.

六、

这个代码有不错的参考价值，特别是 case 最开始赋值那里。