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Aquantia Datasheet

December 2017

AQR107-AQR109

AQrate® Multi-Gigabit Ethernet PHY Transceiver

AQR107-AQR109 Revision 1.2.4 - December 2017

Strictly Confidential

General Description

The Aquantia

AQR107-AQR109 AQrate PHYs are low-power, full-reach, high-performance, multi-gigabit

(10GBASE-T/5GBASE-T/2.5GBASE-T/1000BASE-T/100BASE-TX) Ethernet PHY transceivers. Aquantia

AQrate PHYs are compliant with both the IEEE

802.3an/bz standard and the

NBASE-T

™

Alliance PHY

Specification to perform all of the physical layer functions required to implement 10GBASE-T/5GBASE-T/

2.5GBASE-T/1000BASE-T/100BASE-TX transmission over 100+ meters of twisted pair cabling. The AQrate

PHY family integrates such features as Energy Efficient Ethernet (EEE), Precision Time Protocol (PTP)/1588v2,

IEEE MAC Security (MACsec), supports all PoE standards up to 100W, and supports jumbo packets up to 16KB

in all operating modes.

The AQR107-AQR109 are pin-compatible, multi-gigabit PHYs housed in compact 7 mm x 11 mm flip-chip BGA

packages and operate over both the Extended (0

C to +108

C) and Industrial (-40

C to +108

C) temperature

ranges. Unless otherwise noted, the datasheet describes 5-speed operation and functionality.

Features Benefits

• AQR107: 10GBASE-T/5GBASE-T/2.5GBASE-T/1000BASE-T/100BASE-TX

• AQR108: 5GBASE-T/2.5GBASE-T/1000BASE-T/100BASE-TX

• AQR109: 2.5GBASE-T/1000BASE-T/100BASE-TX

• Pin-compatible multi-gigabit PHYs (5-speed/4-speed/3-speed)

enable design flexibility and reuse

• IEEE 802.3an/bz and NBASE-T featuring AQrate technology

o 10GBASE-T: 100 meters over Augmented Cat 6 (Cat 6A) and Cat 7, 55

meters over Cat 6, and best effort over Cat 5e

o 5GBASE-T, 2.5GBASE-T: over 100 meters of Cat 5e or better cabling

• Ability to support highest data rate possible with a given cable

environment while reducing power and latency

• 5G and 2.5G operation over legacy infrastructure, while

delivering backward compatibility with existing equipment

• 2.7W typical 10GBASE-T operating power per port

o 30 meters of Cat 6A UTP

• 2.3W typical 5GBASE-T operating power per port

• 1.9W typical 2.5GBASE-T operating power per port

• Enables efficient high-density design for high port-count and

compact switches across a range of speed requirements

• Energy-Efficient Ethernet (EEE)

• MACsec (IEEE 802.1ae, MAC security standard)

o Full support for Advanced Encryption Standard (AES-256) and

stand-alone operation

• PTP/1588v2

• Synchronous Ethernet (Sync-E), ITU-T standard in cooperation with IEEE

• EEE lowers overall power consumption and lowers equipment

operating costs

• MACsec provides for secure, encrypted data communications

across networks

• PTP/1588v2 provides for timing accuracy across the network

• Sync-E synchronizes clock signals on the PCB

• Integrated Wake-on-LAN (WoL) Support

o Compliant to Microsoft Network Device Class specification

• Energy Detect

o Places PHY in a low-power state when there is no active link partner

• Integrated packet filtering enables sub-1W support in

100BASE-TX mode

• Provides additional power savings when no active link partner is

present

• Built-in Thermal Management

o On-chip thermal sensor with alarm and warning thresholds

• Enables deployment in thermally constrained environments

• 7 mm x 11 mm flip-chip 104-pin BGA package

o 0.8 mm ball pitch

o Low thermal resistance

• Low cost

• Flexible heat-sinking

• Compatible with volume PCB manufacturing

• IEEE ® 802.3-2012 compliant auto-negotiation • Interoperable with existing Ethernet infrastructure

• External SPI FLASH interface with optional FLASH-less operation

o At-manufacture FLASH burn capability

• Reduces BOM cost as one or no FLASH devices required

• Enables firmware download/upgrade and FLASH image loading

during manufacturing

Aquantia Corp. 3

Aquantia Datasheet

December 2017

AQrate® Multi-Gigabit Ethernet PHY Transceiver

AQR107-AQR109

AQR107-AQR109 Revision 1.2.4 - December 2017

Strictly Confidential

This data is then mapped into a virtual internal XGMII interface where blocks of two XGMII frames (32 bits of data

+ 4 bits of control) are encoded into a single 65B block, using the 64B/65B encoding scheme specified in Clause

55. In 10G mode, fifty of these 65B blocks are aggregated together, along with a prepended auxiliary bit, and an

appended CRC-8 to form the 3259-bit 10GBASE-T transmission frame payload.

This payload is encoded using a combination of LDPC encoding and coset partitioning, with the LDPC encoding

adding an additional 325 systematic check bits to produce a 3584-bit 10GBASE-T transmission frame. The coset

partitioning effectively divides the frame up into 512 7-bit symbols, where the upper 3 bits are uncoded and

describe the coset, while the lower 4 bits are coded and identify an element within the coset.

These 8 cosets are then mapped onto a 128-DSQ constellation (a 16 x 16 checkerboard pattern) which is

physically encoded as two back-to-back PAM-16 symbols. These symbols are then THP precoded, filtered, and

sent out over the four twisted pairs in the cable. AQrate 5G transmission is done in a similar fashion, but uses a

fully LDPC encoded 320ns PAM-16 frame containing twenty-five 65B blocks. AQrate 2.5G transmission is also

similar, but uses a 640ns frame containing twenty-five 65B blocks.

In the receive direction in 10G, 5G, and 2.5G modes, PAM-16 coded symbols enter the AQR107-AQR109 from the

line interface and pass through the hybrid, which provides transmit / receive isolation. These symbols are then

filtered and amplified prior to being sampled by four high-speed, high-precision A/D converters. The outputs of

these A/D converters are then passed through an extensive set of adaptive equalizers which provide both

cross-talk and echo cancellation. After timing is recovered, the data from the four channels is aligned and merged

together to form the original, but noisy transmission frames.

In all three modes, the data is decoded using an LDPC decoder. However, in 10G mode the data is further sliced

using knowledge of the coset partitioning and 128-DSQ mapping to produce the original 10GBASE-T transmission

frame payload. The CRC-8 over this payload is then checked to ensure integrity of the uncoded bits. Finally, in all

schemes, the auxiliary bit is stripped, the 65B blocks remapped into XGMII blocks, and the received Ethernet data

transmitted out the MAC interface.

When operating in 1G or 100M modes, receive data from the analog front-end is routed to either the 1G or 100M

PCS where timing is recovered and equalization performed. In 1G mode, Viterbi decoding is also done. From here,

the data passes across a virtual GMII interface to the system interface which is either SGMII, or USXGMII mode on

logical Lane 0.

In the transmit direction, 1G or 100M data is received on either the SGMII, or USXGMII interface, passed through

the 1G or 100M PCS and then transmitted by the common analog front-end. Figure 2 shows a typical system-level

block diagram of a 10GBASE-T channel built using the AQR107-AQR109.

Figure 2 AQR107-AQR109 System Block Interconnect

PHY

MAC I/F Line

ICM

SPI

MDIO & Control

MAC

Serial

FLASH

50 MHz

Power

Supply

Aquantia Datasheet

December 2017

AQrate® Multi-Gigabit Ethernet PHY Transceiver

AQR107-AQR109

4 Aquantia Corp.

AQR107-AQR109 Revision 1.2.4 - December 2017

Strictly Confidential

On the line side of the AQR107-AQR109, a robust interface providing good common-mode rejection and electrical

protection against cable discharge is implemented. On the MAC side, the AQR107-AQR109 provides a robust

SerDes interface with configurable pre-emphasis and receive equalization. For test coverage, this interface also

incorporates AC JTAG.

Control over the chip is done via an external C-language application program interface (API) that provides an

easy-to-use abstraction of the AQR107-AQR109, and via an MDIO interface provides the standard Clause 45

On-chip, the AQR107-AQR109 contains a 32-bit microcontroller which manages the state machines and operation

of the various elements within the chip. Consequently, there is a great deal of flexibility afforded to the end user

because of the presence of this microcontroller, and as such the AQR107-AQR109 offers a high degree of control

and flexibility. The image for the microcontroller is stored either in an optional external SPI FLASH, or loaded at

boot time via the MDIO interface (MDIO boot-load).

This interface also provides the user the capability of directly programming the FLASH during manufacturing. In

addition to the Ethernet interfaces, the AQR107-AQR109 provides three 20mA LED outputs for the port that are

software configurable to respond to a variety of conditions such as link activity and connection status. Clocking for

AQR107-AQR109 is provided from a 50MHz external crystal or differential clock.

To better assist the system designer in deploying the AQR107-AQR109, a reference design (with part numbers,

schematics, and layout) is provided that is optimized for performance, efficiency, and cost. Power for the

AQR107-AQR109 is provided from three supply voltages, and supports I/O voltage levels of 1.8V and 3.3V.

Package Information

The AQR107-AQR109 is packaged in a 0.8 mm pitch, 7 mm x 11 mm over-molded flip-chip BGA (8 rows

x 13 rows). The package is marked as shown in Figure 3, and is described in Table 1 on page 5.

Figure 3 Part Marking

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