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Page 1 Zynq ZedBoard Concepts, Tools, and Techniques 8/7/2013

ZedBoard: Zynq-7000

AP SoC Concepts,

Tools, and Techniques

A Hands-On Guide to

Effective Embedded System

Design

ZedBoard (Vivado 2013.2)

Notice of Disclaimer

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx

products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all

faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR

PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory

of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials

(including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or

damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action

brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the

possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of

updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the

Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited

Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and

support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-

safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx

products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.

Page 3 Zynq ZedBoard Concepts, Tools, and Techniques 8/7/2013

Table of Contents

Chapter 1 Introduction ................................................................................................... 7

1.1 About this Guide .................................................................................................. 7

1.1.1 Take a Test Drive! .......................................................................... 8

1.1.2 Additional Documentation ............................................................................ 8

1.2 How Zynq AP SoC and Xilinx software Simplify Embedded Processor Design 9

1.3 What You Need to Set Up Before Starting ........................................................ 11

1.3.1 Software Installation Requirements: ........................................................... 11

1.3.2 Hardware Requirements for this Guide ...................................................... 12

Chapter 2 Embedded System Design Using the Zynq Processing System ................. 13

2.1 Embedded System Construction ........................................................................ 15

2.1.1 Take a Test Drive! Creating a New Embedded Project With a Zynq

Processing System .................................................................................................... 15

2.1.2 Take a Test Drive! Running the “Hello World” Application ........ 25

2.1.3 Additional Information ............................................................................... 30

Chapter 3 Embedded System Design Using the Zynq Processing System and

Programmable Logic ......................................................................................................... 31

3.1 Adding soft IP in the PL to interface with the Zynq PS ..................................... 31

3.1.1 Take a Test Drive! Check Functionality of IP instantiated in the PL

3.1.2 Take a Test Drive! Working with SDK ......................................... 39

Chapter 4 Debugging with SDK and Vivado Logic Analyzer .................................... 41

4.1 Take a Test Drive! Debugging with Software, Using SDK ................. 41

4.2 Take a Test Drive! Debugging Hardware Using Vivado Logic Analyzer

tool 43

Chapter 5 Booting Linux and Application Debugging Using SDK ............................ 50

5.1 Requirements ...................................................................................................... 50

5.2 Booting Linux on a ZedBoard ............................................................................ 51

5.2.1 Boot Methods .............................................................................................. 51

5.2.2 Booting Linux from JTAG.......................................................................... 52

5.2.3 Take a Test Drive! Booting Linux in JTAG Mode ....................... 53

5.2.4 Booting Linux from QSPI Flash ................................................................. 56

5.2.5 Take a Test Drive! Booting Linux from QSPI Flash .................... 56

5.2.6 Booting Linux from the SD Card................................................................ 60

5.2.7 Take a Test Drive! Booting Linux from the SD Card ................... 60

5.3 Hello World Example......................................................................................... 61

5.3.1 Take a Test Drive! Running a “Hello World” Application ........... 61

5.4 Controlling LEDs and Switches in Linux Example .......................................... 68

Page 5 Zynq ZedBoard Concepts, Tools, and Techniques 8/7/2013

Table of Figures

Figure 1-1: The ZedBoard Zynq Evaluation and Development Kit ................................... 7

Figure 2-1: Vivado Design Flow for Zynq ....................................................................... 13

Figure 2-2: New Project Wizard Part Selection ................................................................ 16

Figure 2-3: Vivado GUI .................................................................................................... 17

Figure 2-4: Blank Block Diagram view ............................................................................ 18

Figure 2-5: IP Catalog ....................................................................................................... 18

Figure 2-6: Processing System Block in the Block Diagram view ................................... 19

Figure 2-7: Processing System Re-customize IP view ..................................................... 20

Figure 2-8: Processing System 7....................................................................................... 21

Figure 2-9: Sources pane showing the system.bd file....................................................... 22

Figure 2-10: The SDK GUI ............................................................................................. 23

Figure 2-11: Address Map in SDK system.xml Tab......................................................... 24

Figure 2-12: ZedBoard Power switch and Jumper settings ........................................ 25

Figure 2-13: Serial Terminal Settings ............................................................................... 26

Figure 2-14: New Application Project Wizard ................................................................. 27

Figure 2-15: Hello World from Available Templates....................................................... 28

Figure 2-16: Successful Build ........................................................................................... 29

Figure 2-17: "Hello World" on the Serial Terminal ......................................................... 30

Figure 3-1: System Design Overview ............................................................................... 32

Figure 3-2: Connecting ports on two IP blocks ................................................................ 34

Figure 3-3: Completed Port Connections ......................................................................... 36

Figure 3-4: Assigned peripheral memory addresses ......................................................... 36

Figure 3-5: Adding a constraints file ................................................................................ 37

Figure 3-6: Constraints file added into project ................................................................. 37

Figure 3-7: Design validation successful .......................................................................... 38

Figure 3-8: Program FPGA Dialog Box ........................................................................... 40

Figure 3-9: Terminal showing application output ............................................................ 40

Figure 4-1: Debug Perspective Suspended ....................................................................... 41

Figure 4-2: Forcing synthesis up-to-date .......................................................................... 44

Figure 4-3: Debug nets in the Debug Perspective ............................................................ 44

Figure 4-4: Set up Debug wizard specifying nets to debug .............................................. 45

Figure 4-5: Trigger Condition Dialog Box ....................................................................... 46

Figure 4-6: Identified devices during Hardware Session .................................................. 47

Figure 4-7: Warning about the debug core not receiving a clock signal .......................... 47

Figure 4-8: Debug Probes available for the waveform view ............................................ 48

Figure 4-9: Captured waveforms from the triggered run .................................................. 49

Figure 5-1: Linux Boot Process on the ZedBoard ............................................................ 53

Figure 5-2: Jumper Settings to boot in JTAG mode ......................................................... 54

Figure 5-3: Creating a Zynq QSPI Boot Image ................................................................ 57

Figure 5-4: Serial Terminal Window showing QSPI programming ................................. 59

Figure 5-5: Serial Terminal Window showing Linux Booting ......................................... 60

Figure 5-6: Jumper Settings to boot from SD Card .......................................................... 61

Figure 5-7: New Project Selection .................................................................................... 62

Figure 5-8: Application Project ........................................................................................ 63

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