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User manual Rev. 2.4 — 11 November 2019 2 of 1149
NXP Semiconductors
UM10912
LPC546xx User manual
Revision history
Rev Date Description
2.4 20191011 LPC546xx User manual.
Modifications:
• Updated Section 5.6.8 with new content for Table 80 “Pointer to ISP parameter array”.
2.3 20190617 LPC546xx User manual.
Modifications: • Updated Section 5.5.5 with new content for 5.5.1 thru 5.5.4.
2.2 20181029 LPC546xx User manual.
Modifications:
• Updated command identifier of Write subblock and Read subblock to 0xAC and 0xAD. See
Table 33 “
I2C / SPI command summary”.
• Added text to Section 5.4.5.15 “ISP ReadUID”.
• Added text to Section 5.6.9 “Read unique ID number”.
• Added remark to Section 7.5.72 “EMC clock delay control register”.
• Changed reset value of BODRSTENA in Ta ble 241 “BOD control register (BODCTRL, other system
registers: offset 0x044) bit description” to 1.
• Updated text in Section 8.3.4 “Deep-sleep mode”: In deep-sleep mode, the system clock to the
processor is disabled as in sleep mode. All analog blocks are powered down by default but can be
selected to keep running through the power API if needed as wake-up sources. The main clock and
all peripheral clocks are disabled by default.
• Updated Ta ble 9 07 “USB Host pin description”: USB0_PORTPWRN and
USB0_OVERCURRENTN.
• Updated Table 1078 “ISP-AP commands”.
• Added Section 49.8 “Debug memory re-mapping”.
2.1 20171109 LPC546xx User manual.
Modifications:
• Updated Table 260 “Register overview: Input multiplexing (base address 0x4000 5000)”. Fixed
cross references of SCT0_INMUX0 to SCT0_INMUX6.
• Updated Section 16.3 “Basic configuration”. Added a remark: The maximum frequency for the
SCTimer/PWM clock is 100 MHz. Added the remark to Section 7.5.41 “SCTimer/PWM clock select
register”.
• Updated Table 1 “Ordering information” and Table 2 “Ordering options”. Added the part numbers:
LPC54605J256BD100, LPC54605J512BD100, LPC54605J256ET100, LPC54605J512ET100.
• Updated Table 232 “Device ID0 register values”.
• Added text to Section 15.5.2 “DMA Modes”:
Using any specific DMA channel requires initializing the device registers associated with that
channel (see Table 300), and setting the channel descriptor. The channel descriptor is shown in
Table 303. The channel descriptor is an entry in the channel descriptor table. This table is located
somewhere in memory, typically in on-chip SRAM (see Section 15.6.3 “SRAM Base address
register”).
The DMA transfer is initiated by writing the channels CFG and XFERCFG registers and setting the
channels ENABLESET bit. Note that once a DMA operation is initiated, the descriptor entry in the
DMA descriptor table may be modified by the DMA controller. Therefore, when a subsequent DMA
transaction is initiated, the DMA descriptor entry must be re-initialized. This is not the case with the
linked descriptors. The linked list entries, that are not in the main DMA descriptor table, do not need
to be re-written, for subsequent DMA requests. These entries are not modified by the controller.
• Added Chapter 4 “LPC546xx FRO API ROM routine”.
• Added bit 14 to Section 7.5.77 “FRO Control register”.
2.0 20170726 LPC546xx User manual.
