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cs8900硬件手册

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CS8900A

Product Data Sheet

Crystal LAN™ Ethernet

Controller

FEATURES

z Single-Chip IEEE 802.3 Ethernet Controller with

Direct ISA-Bus Interface

Maximum Current Consumption = 55 mA (5V

Supply

)

z 3V or 5V Operation

z Industrial Temperature Range

z Comprehensive Suite of Software Drivers

Available

z Efficient PacketPage™ Architecture Operates in

I/O and Memory Space, and as DMA Slave

z Full Duplex Operation

z On-Chip RAM Buffers Transmit and Receive

Frames

z 10BASE-T Port with Analog Filters, Provides:

- Automatic Polarity Detection and Correction

z AUI Port for 10BASE2, 10BASE5 and 10BASE-F

z Programmable Transmit Features:

- Automatic Re-transmission on Collision

- Automatic Padding and CRC Generation

z Programmable Receive Features:

- Stream Transfer™ for Reduced CPU Overhead

- Auto-Switch Between DMA and On-Chip Memory

- Early Interrupts for Frame Pre-Processing

- Automatic Rejection of Erroneous Packets

z EEPROM Support for Jumperless Configuration

z Boot PROM Support for Diskless Systems

z Boundary Scan and Loopback Test

z LED Drivers for Link Status and LAN Activity

z Standby and Suspend Sleep Modes

DESCRIPTION

The CS8900A is a low-cost Ethernet LAN Controller op-

timized for the Industry Standard Architecture (ISA) bus

and general purpose microcontroller busses. Its highly-

integrated design eliminates the need for costly external

components required by other Ethernet controllers. The

CS8900A includes on-chip RAM, 10BASE-T transmit

and receive filters, and a direct ISA-Bus interface with

24 mA Drivers.

In addition to high integration, the CS8900A offers a

broad range of performance features and configuration-

options. Its unique PacketPage architecture

automatically adapts to changing network traffic pat-

terns and available system resources. The result is

increased system efficiency.

The CS8900A is available in a 100-pin LQFP package

ideally suited for small form-factor, cost-sensitive Ether-

net applications. With the CS8900A, system engineers

can design a complete Ethernet circuit that occupies

less than 1.5 square inches (10 sq. cm) of board space.

ORDERING INFORMATION

CS8900A-CQ 0° to 70° C 5V LQFP-100

CS8900A-CQZ 0° to 70° C 5V LQFP-100 Lead free

CS8900A-IQ -40° to 85° C 5V LQFP-100

CS8900A-IQZ -40° to 85° C 5V LQFP-100 Lead free

CS8900A-CQ3 0° to 70° C 3.3V LQFP-100

CS8900A-CQ3Z 0° to 70° C 3.3V LQFP-100 Lead free

CS8900A-IQ3 -40° to 85° C 3.3V LQFP-100

CS8900A-IQ3Z -40° to 85° C 3.3V LQFP-100 Lead free

CRD8900A-1 Evaluation Kit

EEPROM

RJ-45 10BASE-T

Attachment

Unit

Interface

(AUI)

20 MHz

XTAL

RAM

Bus

Logic

Memory

Manager

802.3

MAC

Engine

EEPROM

Control

Encoder/

Decoder

PLL

10BASE-T

RX Filters &

Receiver

10BASE-T

TX Filters &

Transmitter

AUI

Transmitter

AUI

Collision

AUI

Receiver

Clock

Power

Manager

Boundary

Scan

Test Logic

LED

Control

CS8900A ISA Ethernet Controller

Host

Host Bus

DS271F4 AUG ‘07

2 DS271F4

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

TABLE OF CONTENTS

1.0 INTRODUCTION ......................................................................................................................8

1.1 General Description ...........................................................................................................8

1.1.1 Direct ISA-Bus Interface .......................................................................................8

1.1.2 Integrated Memory ...............................................................................................8

1.1.3 802.3 Ethernet MAC Engine .................................................................................8

1.1.4 EEPROM Interface ...............................................................................................8

1.1.5 Complete Analog Front End .................................................................................8

1.2 System Applications ..........................................................................................................8

1.2.1 Motherboard LANs ...............................................................................................8

1.2.2 Ethernet Adapter Cards ........................................................................................9

1.3 Key Features and Benefits ..............................................................................................10

1.3.1 Very Low Cost ....................................................................................................10

1.3.2 High Performance ...............................................................................................10

1.3.3 Low Power and Low Noise .................................................................................10

1.3.4 Complete Support ...............................................................................................10

2.0 PIN DESCRIPTION .............................................................................................................12

3.0 FUNCTIONAL DESCRIPTION ...............................................................................................17

3.1 Overview .........................................................................................................................17

3.1.1 Configuration ......................................................................................................17

3.1.2 Packet Transmission ..........................................................................................17

3.1.3 Packet Reception ...............................................................................................17

3.2 ISA Bus Interface ............................................................................................................18

3.2.1 Memory Mode Operation ....................................................................................18

3.2.2 I/O Mode Operation ............................................................................................18

3.2.3 Interrupt Request Signals ...................................................................................18

3.2.4 DMA Signals .......................................................................................................18

3.3 Reset and Initialization ....................................................................................................19

3.3.1 Reset ..................................................................................................................19

3.3.1.1 External Reset, or ISA Reset ...............................................................19

3.3.1.2 Power-Up Reset ..................................................................................19

3.3.1.3 Power-Down Reset ..............................................................................19

3.3.1.4 EEPROM Reset ...................................................................................19

3.3.1.5 Software Initiated Reset .......................................................................19

3.3.1.6 Hardware (HW) Standby or Suspend ..................................................19

3.3.1.7 Software (SW) Suspend ......................................................................19

3.3.2 Allowing Time for Reset Operation .....................................................................20

3.3.3 Bus Reset Considerations ..................................................................................20

3.3.4 Initialization .........................................................................................................20

3.4 Configurations with EEPROM .........................................................................................21

3.4.1 EEPROM Interface .............................................................................................21

3.4.2 EEPROM Memory Organization .........................................................................21

3.4.3 Reset Configuration Block ..................................................................................21

3.4.3.1 Reset Configuration Block Structure ....................................................22

3.4.3.2 Reset Configuration Block Header ......................................................22

3.4.3.3 Determining the EEPROM Type ..........................................................23

3.4.3.4 Checking EEPROM for presence of Reset Configuration Block ..........23

3.4.3.5 Determining Number of Bytes in the Reset Configuration Block .........23

3.4.4 Groups of Configuration Data .............................................................................23

3.4.4.1 Group Header ......................................................................................23

3.4.5 Reset Configuration Block Checksum ................................................................24

3.4.6 EEPROM Example .............................................................................................24

3.4.7 EEPROM Read-out ............................................................................................24

DS271F4 3

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

3.4.7.1 Determining EEPROM Size .................................................................24

3.4.7.2 Loading Configuration Data ................................................................. 24

3.4.8 EEPROM Read-out Completion .........................................................................24

3.5 Programming the EEPROM ............................................................................................ 25

3.5.1 EEPROM Commands ........................................................................................25

3.5.2 EEPROM Command Execution .........................................................................25

3.5.3 Enabling Access to the EEPROM ......................................................................26

3.5.4 Writing and Erasing the EEPROM ..................................................................... 26

3.6 Boot PROM Operation ....................................................................................................26

3.6.1 Accessing the Boot PROM ................................................................................. 26

3.6.2 Configuring the CS8900A for Boot PROM Operation ........................................26

3.7 Low-Power Modes ..........................................................................................................27

3.7.1 Hardware Standby ..............................................................................................27

3.7.2 Hardware Suspend ............................................................................................. 27

3.7.3 Software Suspend ..............................................................................................27

3.8 LED Outputs ....................................................................................................................29

3.8.1 LANLED .............................................................................................................29

3.8.2 LINKLED or HC0 ................................................................................................ 29

3.8.3 BSTATUS or HC1 ..............................................................................................29

3.8.4 LED Connection ................................................................................................. 29

3.9 Media Access Control .....................................................................................................29

3.9.1 Overview ............................................................................................................29

3.9.2 Frame Encapsulation and Decapsulation ........................................................... 30

3.9.2.1 Transmission .......................................................................................30

3.9.2.2 Reception ............................................................................................30

3.9.2.3 Enforcing Minimum Frame Size ..........................................................31

3.9.3 Transmit Error Detection and Handling ..............................................................31

3.9.3.1 Loss of Carrier .....................................................................................31

3.9.3.2 SQE Error ............................................................................................ 31

3.9.3.3 Out-of-Window (Late) Collision ............................................................ 31

3.9.3.4 Jabber Error ........................................................................................31

3.9.3.5 Transmit Collision ................................................................................31

3.9.3.6 Transmit Underrun .............................................................................. 32

3.9.4 Receive Error Detection and Handling ............................................................... 32

3.9.4.1 CRC Error ............................................................................................32

3.9.4.2 Runt Frame ......................................................................................... 32

3.9.4.3 Extra Data ........................................................................................... 32

3.9.4.4 Dribble Bits and Alignment Error .........................................................32

3.9.5 Media Access Management ............................................................................... 32

3.9.5.1 Collision Avoidance ............................................................................. 32

3.9.5.2 Two-Part Deferral ................................................................................33

3.9.5.3 Simple Deferral .................................................................................... 33

3.9.5.4 Collision Resolution .............................................................................34

3.9.5.5 Normal Collisions ................................................................................34

3.9.5.6 Late Collisions ..................................................................................... 34

3.9.5.7 Backoff ................................................................................................34

3.9.5.8 Standard Backoff .................................................................................34

3.9.5.9 Modified Backoff .................................................................................. 35

3.9.5.10 SQE Test ...........................................................................................35

3.10 Encoder/Decoder (ENDEC) ..........................................................................................35

3.10.1 Encoder ............................................................................................................35

3.10.2 Carrier Detection ..............................................................................................36

3.10.3 Clock and Data Recovery ................................................................................. 36

4 DS271F4

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

3.10.4 Interface Selection ............................................................................................36

3.10.4.1 10BASE-T Only .................................................................................36

3.10.4.2 AUI Only ............................................................................................36

3.10.4.3 Auto-Select ........................................................................................36

3.11 10BASE-T Transceiver ..................................................................................................36

3.11.1 10BASE-T Filters ..............................................................................................37

3.11.2 Transmitter .......................................................................................................37

3.11.3 Receiver ...........................................................................................................37

3.11.3.1 Squelch Circuit ...................................................................................37

3.11.3.2 Extended Range ................................................................................38

3.11.4 Link Pulse Detection .........................................................................................38

3.11.5 Receive Polarity Detection and Correction .......................................................38

3.11.6 Collision Detection ............................................................................................39

3.12 Attachment Unit Interface (AUI) ....................................................................................39

3.12.1 AUI Transmitter .................................................................................................39

3.12.2 AUI Receiver ....................................................................................................39

3.12.3 Collision Detection ............................................................................................39

3.13 External Clock Oscillator ...............................................................................................40

4.0 PACKETPAGE ARCHITECTURE..........................................................................................41

4.1 PacketPage Overview .....................................................................................................41

4.1.1 Integrated Memory .............................................................................................41

4.1.2 Bus Interface Registers ......................................................................................41

4.1.3 Status and Control Registers ..............................................................................41

4.1.4 Initiate Transmit Registers ..................................................................................41

4.1.5 Address Filter Registers .....................................................................................41

4.1.6 Receive and Transmit Frame Locations .............................................................41

4.2 PacketPage Memory Map ...............................................................................................42

4.3 Bus Interface Registers ...................................................................................................44

4.4 Status and Control Registers ..........................................................................................49

4.4.1 Configuration and Control Registers ...................................................................49

4.4.2 Status and Event Registers ................................................................................49

4.4.3 Status and Control Bit Definitions .......................................................................50

4.4.3.1 Act-Once Bits .......................................................................................50

4.4.3.2 Temporal Bits .......................................................................................50

4.4.3.3 Interrupt Enable Bits and Events .........................................................50

4.4.3.4 Accept Bits ...........................................................................................51

4.4.4 Status and Control Register Summary ...............................................................51

4.5 Initiate Transmit Registers ...............................................................................................69

4.6 Address Filter Registers ..................................................................................................71

4.7 Receive and Transmit Frame Locations ..........................................................................72

4.7.1 Receive PacketPage Locations ..........................................................................72

4.7.2 Transmit Locations .............................................................................................72

4.8 Eight and Sixteen Bit Transfers .......................................................................................72

4.8.1 Transferring Odd-Byte-Aligned Data ..................................................................73

4.8.2 Random Access to CS8900A Memory ...............................................................73

4.9 Memory Mode Operation .................................................................................................73

4.9.1 Accesses in Memory Mode .................................................................................73

4.9.2 Configuring the CS8900A for Memory Mode ......................................................74

4.9.3 Basic Memory Mode Transmit ............................................................................74

4.9.4 Basic Memory Mode Receive .............................................................................75

4.9.5 Polling the CS8900A in Memory Mode ...............................................................75

4.10 I/O Space Operation ......................................................................................................75

4.10.1 Receive/Transmit Data Ports 0 and 1 ...............................................................75

DS271F4 5

CS8900A

Crystal LAN™ Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

4.10.2 TxCMD Port ...................................................................................................... 75

4.10.3 TxLength Port ................................................................................................... 76

4.10.4 Interrupt Status Queue Port ............................................................................. 76

4.10.5 PacketPage Pointer Port ..................................................................................76

4.10.6 PacketPage Data Ports 0 and 1 .......................................................................76

4.10.7 I/O Mode Operation .......................................................................................... 76

4.10.8 Basic I/O Mode Transmit .................................................................................. 76

4.10.9 Basic I/O Mode Receive ................................................................................... 77

4.10.10 Accessing Internal Registers ..........................................................................77

4.10.11 Polling the CS8900A in I/O Mode ................................................................... 77

5.0 OPERATION ..........................................................................................................................78

5.1 Managing Interrupts and Servicing the Interrupt Status Queue ...................................... 78

5.2 Basic Receive Operation ................................................................................................. 78

5.2.0.1 Overview .............................................................................................78

5.2.1 Terminology: Packet, Frame, and Transfer ........................................................80

5.2.1.1 Packet .................................................................................................80

5.2.1.2 Frame ..................................................................................................80

5.2.1.3 Transfer ...............................................................................................80

5.2.2 Receive Configuration ........................................................................................80

5.2.2.1 Configuring the Physical Interface ....................................................... 81

5.2.2.2 Choosing which Frame Types to Accept .............................................81

5.2.2.3 Selecting which Events Cause Interrupts ............................................ 81

5.2.2.4 Choosing How to Transfer Frames ...................................................... 81

5.2.3 Receive Frame Pre-Processing .........................................................................82

5.2.3.1 Destination Address Filtering .............................................................. 82

5.2.3.2 Early Interrupt Generation ................................................................... 82

5.2.3.3 Acceptance Filtering ............................................................................ 83

5.2.3.4 Normal Interrupt Generation ................................................................83

5.2.4 Held vs. DMAed Receive Frames ...................................................................... 83

5.2.5 Buffering Held Receive Frames .........................................................................85

5.2.6 Transferring Held Receive Frames ....................................................................85

5.2.7 Receive Frame Visibility .....................................................................................85

5.2.8 Example of Memory Mode Receive Operation ...................................................86

5.2.9 Receive Frame Byte Counter ............................................................................. 86

5.2.10 Receive Frame Address Filtering ..................................................................... 87

5.2.10.1 Individual Address Frames ................................................................87

5.2.10.2 Multicast Frames ............................................................................... 87

5.2.10.3 Broadcast Frames .............................................................................87

5.2.11 Configuring the Destination Address Filter .......................................................87

5.2.12 Hash Filter ........................................................................................................88

5.2.12.1 Hash Filter Operation ........................................................................88

5.2.13 Broadcast Frame Hashing Exception ...............................................................88

5.3 Receive DMA ..................................................................................................................90

5.3.1 Overview ............................................................................................................90

5.3.2 Configuring the CS8900A for DMA Operation ....................................................90

5.3.3 DMA Receive Buffer Size ...................................................................................91

5.3.4 Receive-DMA-Only Operation ............................................................................ 91

5.3.5 Committing Buffer Space to a DMAed Frame ....................................................92

5.3.6 DMA Buffer Organization ................................................................................... 92

5.3.7 RxDMAFrame Bit ...............................................................................................92

5.3.8 Receive DMA Example Without Wrap-Around ...................................................92

5.3.9 Receive DMA Operation for RxDMA-Only Mode ...............................................92

5.4 Auto-Switch DMA ............................................................................................................94

剩余137页未读，继续阅读

评论收藏

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xhsytz

2013-09-27

全英文文档很好
wwyk881104

2012-05-24

对CS8900做了详尽的说明，英文原文使用说明书
shaohui973

2013-07-03

不错，值得一读
qq675396274

2013-12-27

全部是英文的，原汁原味，不错
pheffy

2013-05-10

不错的资料，英文版，比中文翻译的好

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liangxfzhang

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