没有合适的资源?快使用搜索试试~ 我知道了~
VCU118的原理图-PDF版本
需积分: 5 26 下载量 167 浏览量
2023-07-09
23:19:25
上传
评论 2
收藏 6.02MB PDF 举报
温馨提示
![preview](https://dl-preview.csdnimg.cn/88026351/0001-29aa1b598e2006bcd9914fab20ffaa9d_thumbnail.jpeg)
![preview-icon](https://csdnimg.cn/release/downloadcmsfe/public/img/scale.ab9e0183.png)
试读
76页
Xilinx的VCU118的原理图,PDF版本,VU9P的FPGA
资源推荐
资源详情
资源评论
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![rar](https://img-home.csdnimg.cn/images/20210720083606.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![zip](https://img-home.csdnimg.cn/images/20210720083736.png)
![7z](https://img-home.csdnimg.cn/images/20210720083312.png)
![](https://csdnimg.cn/release/download_crawler_static/88026351/bg1.jpg)
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE:
76
ASSY P/N: 0432092
HW-U1-VCU118_REV2_0
Title Page
SCHEM, ROHS COMPLIANT
15/07/2017:01:45
PCB P/N: 1280906
DN
SCH P/N: 0381739
TEST P/N: TSS0185
1
03
2.0
THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY
DOCUMENTATION.
INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF
CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT
STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF
KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR
XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC,
AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE IN
THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES.
YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST,
OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING,
BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING,
OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX.
XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OF
THE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION,
TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES
NO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, OR
TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY
DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR
ASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE
THE DOCUMENTATION.
THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")
ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH
CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY
DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT
IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET.
ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY
APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY
DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL
RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE
("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT
THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
DISCLAIMER:
VCU118 EVALUATION BOARD HW-U1-VCU118
(XCVU9P-2FLGA2104)
Title Page
![](https://csdnimg.cn/release/download_crawler_static/88026351/bg2.jpg)
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE:
HW-U1-VCU118_REV2_0
ASSY P/N: 0432092
2.0
SCHEM, ROHS COMPLIANT
TEST P/N: TSS0185
PCB P/N: 1280906
15/07/2017:01:45
DN
03
Block Diagram
2 76
SCH P/N: 0381739
System Controller
BANK 64/70
Page 46-49
QSPI, SD
Pages 60-61
Buffers
VCCINT Regulator @ 80A
11
BANK 66/67 12
Page 67
BANK 65 13
VCC1V8 Regulator @ 10A
Page 62
MGT120-127 14-15
BANK# PAGE#
Page 64
VADJ_1V8 Regulator @ 10A
Page 65
BANK 0
BANK#
MGTAVCC Regulator @ 17A
MGTAVTT Regulator @ 17A
Page 72
SYS_2V5 Regulator @ 2A
Page 66
VCC1V2 Regulator @ 10A
Page 68
MGTVCCAUX 2 X Regulator @ 1A
SMT, 14-pin JTAG
Page 24
PAGE#
Page 70
UTIL_1V35 Regulator @ 10A
Page 50
BANK 41
BANK 46/48
MGT224-227
Page 69
MECHANICALS
BANK 40/42
PWR/GND BANKS
UTIL_3V3 Regulator @ 17A
4
5
3
BANK 47
BANK 72/73
BANK 43/45
BANK 71
PCIe Edge x16
PWR SYSTEM
Page 71
SYS_1V0 Regulator @ 2A
6
MGT231-2338
10
9
7
17
12VDC
16
Page 76
18-23
59-75
Page 55-57
Page 43
HP
Page 50
QSFP2+
Clocks & Clk. Buffers
Page 44-45
Page 73
BPI Flash
UART, EEPROM
SW,LEDs,PMODs,L/S
BPI FLASH 16-Bit
RLD3 C3 2x36
QSFP1+
Page 39-42
FMC HPC 1
Page 59
DRAM_C2_VTT Reg. 0.6V @ 3A
Page 74
RLD3_C3_VTERM_0V6 Reg. 0.6V @ 3A
Page 73
DRAM_C1_VTT Reg. 0.6V @ 3A
Page 51
IIC Mux
Ethernet PHY
Page 52-53
Page 63
VCCINTIO_BRAM Regulator @ 10A
SYS_2V2 Regulator @ 1A
SYS_1V8 Regulator @ 1A
FMCP HSPC
QSFP Ctrl
EthernetPHY I/F
USB UART I/F
GPIO PB I/F
FireFly Ctrl
REF
Page 50
REF
REF
Page 54
FIREFLY
FMCP HSPC MGTs
Page 34
HPHPHPHPHPHP
HP
HP HP
HPHP HP
7371 46
4367
70
47
U1
GTY224
GTY233
GTY232
GTY231
GTY227
GTY226
GTY225
XCVU9P-L2FLGA2104
72
HP
45
HP
424041646566
48
HP
GTY120
GTY121
GTY122
GTY127
GTY126
GTY125
Page 31-33
Page 28-30
DDR4 C2 80-bit
5 Components
Page 25-27
DDR4 C1 80-bit
5 Components 2 Components
Page 34-38
Page 54
Page 58
QSFP+ Clock Recovery
Block Diagram
![](https://csdnimg.cn/release/download_crawler_static/88026351/bg3.jpg)
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE:
SCHEM, ROHS COMPLIANT
3
FPGA Bank 0
2.0
HW-U1-VCU118_REV2_0
76
SCH P/N: 0381739
ASSY P/N: 0432092
TEST P/N: TSS0185
PCB P/N: 1280906
15/07/2017:01:45
DN
03
UTIL_3V3
UTIL_3V3
GND
1%
261
1
2
1/10W
R472
GND
GND
1/10W
1%
1
R473
261
2
GND
VCC1V8
1/16W
1%
R115
4.70K
1
2
1TS518FE_FL35E
2
B1
BAT_TS518_TS621_DUAL
UTIL_3V3
GRN
RED
2
DS2
4 3
LED-GRN-RED
1
4.70K
1/16W
1%
R116
2
1
VCC1V8
R547
2
1
DNP
VCC1V8_FPGA
GND
DIR
VCCB
B
VCCA
GND
A
2
3
5
SC70_6
SN74AVC1T45
6 1
4
U53
GND
DNP
R418
2
1
SYS_1V8
2
1
1%
R1083
1.21K
1/10W
GND
GND
R548
1
1%
1.00K
2
1/16W
1%
1/16W
R560
1.00K
1
2
GND
GND
4
HDR_1X4
3
2
1
J78
GND
D15
3
2
BAS40-04
1
200MW
40V
VCC1V8
VCC1V8
R553
200
1/10W
1%
1
2
1%
R554
2
1/10W
200
1
0.1UF
25V 2
C540
1
25V
C633
0.1UF
2
1
HDR_1X3
1
2
J5
3
VCCINT_FPGA
VCC1V8_FPGA
R1291
1.00K
1/16W
1
2
1%
1%
4.70K
2
1
R6
1/16W
VCCO_0_AB12
VCCO_0_AH12
M0_0_U10
M1_0_Y11
M2_0_W11
D00_MOSI_0_AP11
D01_DIN_0_AN11
D02_0_AM11
D03_0_AL11
DONE_0_AE12
RSVDGND_AB11
PROGRAM_B_0_AH11
INIT_B_0_AC12
TDI_0_AD15
TDO_0_AD13
TMS_0_AF15
TCK_0_AE13
CCLK_0_AF13
VBATT_AT11
VN_AD17
VP_AC18
VREFP_AD18
VREFN_AC17
DXN_AE17
DXP_AE18
RDWR_FCS_B_0_AJ11
POR_OVERRIDE_AG12
PUDC_B_0_AD12
XCVU9PFLGA2104
BANK 0
AE17
AE18
SOC_VU9P_FLGA2104_IRONWOOD
AJ11
U1
SOC_2104_1MM_IRON
AG12
AD12
AD13
AH11
AL11
AB11
AF13
AE13
AF15
AN11
AD18
AP11
AE12
W11
Y11
U10AB12
AC18
AH12
AM11
AC17
AD17
AT11
AD15
AC12
VCC1V8
GND
1%
1/10W
1.21K
2
R1084
1
1/10W
R1085
1%
1.21K
2
12
1%
1
R1087
1/10W
1.21K
SYS_1V8
4
7
5
63
1
218-4LPSTRF
2
SW16
8
JUMPER_BLOCK_2-PIN
MJB1
VCC1V8_FPGA
1
1/10W
1%
2
10.0K
R16
BAT54T1G
D7
2 1
4.70K
1
2
R236
1%
1/20W
GND
RUM001L02T2CL
150MW
Q2
SOT_723
3
2
1
DS34
1
LED-BLUE-SMT
2
1%
1
2
1/10W
220
R598
FPGA_VBATT
FPGA_VBATT
FPGA_INIT_B
FPGA_INIT_B
PUDC_B_PIN
FPGA_DONE
FPGA_DONE
POR_OVERRIDE_PIN
COMBINED_PGOOD_LS
NC
SYSMON_VP
SYSMON_VP
SYSMON_VN
SYSMON_VN
FPGA_TDO_FMC_TDI
JTAG_TDI
JTAG_TCK
JTAG_TMS
FPGA_PROG_B
COMBINED_PGOOD
FPGA_M2
FPGA_M2
FPGA_M1
FPGA_M1
FPGA_M0
FPGA_M0
SYSCTLR_ENABLE
DXP
DXN
QSPI_CLK
QSPI0_DQ0
QSPI0_DQ1
QSPI0_DQ3
QSPI0_CS_B
QSPI0_DQ2
PCIe Test Header
POR_OVERRIDE select
Default: 2-3 GND
SYSMON I2C Address jumpers
DONE
FPGA Bank 0
![](https://csdnimg.cn/release/download_crawler_static/88026351/bg4.jpg)
GND
1%
2
1/10W
R1073
1
240
VCCO_72_T22
VCCO_72_N21
VCCO_72_K20
VCCO_72_J23
VCCO_72_F22
VCCO_72_C21
VCCO_72_B24
VREF_72_T20
IO_L1P_T0L_N0_DBC_72_P20
IO_L1N_T0L_N1_DBC_72_N20
IO_L2P_T0L_N2_72_N23
IO_L2N_T0L_N3_72_M23
IO_L3P_T0L_N4_AD15P_72_R21
IO_L3N_T0L_N5_AD15N_72_P21
IO_L4P_T0U_N6_DBC_AD7P_72_N22
IO_L4N_T0U_N7_DBC_AD7N_72_M22
IO_L5P_T0U_N8_AD14P_72_R22
IO_L5N_T0U_N9_AD14N_72_P22
IO_L6P_T0U_N10_AD6P_72_T23
IO_L6N_T0U_N11_AD6N_72_R23
IO_T0U_N12_VRP_72_T21
IO_T1U_N12_72_J20
IO_L7P_T1L_N0_QBC_AD13P_72_L23
IO_L7N_T1L_N1_QBC_AD13N_72_K23
IO_L8P_T1L_N2_AD5P_72_K24
IO_L8N_T1L_N3_AD5N_72_J24
IO_L9P_T1L_N4_AD12P_72_M21
IO_L9N_T1L_N5_AD12N_72_L21
IO_L10P_T1U_N6_QBC_AD4P_72_M20
IO_L10N_T1U_N7_QBC_AD4N_72_L20
IO_L11P_T1U_N8_GC_72_K21
IO_L11N_T1U_N9_GC_72_J21
IO_L12P_T1U_N10_GC_72_K22
IO_L12N_T1U_N11_GC_72_J22
IO_L13P_T2L_N0_GC_QBC_72_G22
IO_L13N_T2L_N1_GC_QBC_72_G21
IO_L14P_T2L_N2_GC_72_H23
IO_L14N_T2L_N3_GC_72_H22
IO_L15P_T2L_N4_AD11P_72_E23
IO_L15N_T2L_N5_AD11N_72_E22
IO_L16P_T2U_N6_QBC_AD3P_72_H24
IO_L16N_T2U_N7_QBC_AD3N_72_G23
IO_L17P_T2U_N8_AD10P_72_F21
IO_L17N_T2U_N9_AD10N_72_E21
IO_L18P_T2U_N10_AD2P_72_F24
IO_L18N_T2U_N11_AD2N_72_F23
IO_T2U_N12_72_H20
IO_T3U_N12_72_D21
IO_L19P_T3L_N0_DBC_AD9P_72_E24
IO_L19N_T3L_N1_DBC_AD9N_72_D24
IO_L20P_T3L_N2_AD1P_72_A24
IO_L20N_T3L_N3_AD1N_72_A23
IO_L21P_T3L_N4_AD8P_72_C24
IO_L21N_T3L_N5_AD8N_72_C23
IO_L22P_T3U_N6_DBC_AD0P_72_D22
IO_L22N_T3U_N7_DBC_AD0N_72_C22
IO_L23P_T3U_N8_72_B23
IO_L23N_T3U_N9_72_B22
IO_L24P_T3U_N10_72_B21
IO_L24N_T3U_N11_72_A21
XCVU9PFLGA2104
BANK 72
SOC_VU9P_FLGA2104_IRONWOOD
A21
SOC_2104_1MM_IRON
U1
J21
C24
K21
M20
B22
D22
E22
E23
L21
C22
J22
F21
L20
D21
F24
A23
H24
K22
D24
A24
E21
F23
B23
B21
C23
E24
G23
H22
H20
H23
G21
G22
B24
K23
J20
J24
T20
M21
R21
T23
N23
P20
N22
C21
F22
M22
P22
N20
K24
L23
R22
J23
K20
P21
M23
R23
N21
T22
T21
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE: 2.0
DN
03
15/07/2017:01:45
PCB P/N: 1280906
SCH P/N: 0381739
4
SCHEM, ROHS COMPLIANT
HW-U1-VCU118_REV2_0
FPGA Banks 73 72 C1 DDR4 Data
TEST P/N: TSS0185
76
ASSY P/N: 0432092
VCCO_73_P18
VCCO_73_L17
VCCO_73_H16
VCCO_73_G19
VCCO_73_D18
VCCO_73_A17
VREF_73_T19
IO_L1P_T0L_N0_DBC_73_R18
IO_L1N_T0L_N1_DBC_73_R17
IO_L2P_T0L_N2_73_R19
IO_L2N_T0L_N3_73_P19
IO_L3P_T0L_N4_AD15P_73_M18
IO_L3N_T0L_N5_AD15N_73_M17
IO_L4P_T0U_N6_DBC_AD7P_73_P17
IO_L4N_T0U_N7_DBC_AD7N_73_P16
IO_L5P_T0U_N8_AD14P_73_N19
IO_L5N_T0U_N9_AD14N_73_N18
IO_L6P_T0U_N10_AD6P_73_N17
IO_L6N_T0U_N11_AD6N_73_M16
IO_T0U_N12_VRP_73_T18
IO_T1U_N12_73_L19
IO_L7P_T1L_N0_QBC_AD13P_73_K17
IO_L7N_T1L_N1_QBC_AD13N_73_J16
IO_L8P_T1L_N2_AD5P_73_L16
IO_L8N_T1L_N3_AD5N_73_K16
IO_L9P_T1L_N4_AD12P_73_L18
IO_L9N_T1L_N5_AD12N_73_K18
IO_L10P_T1U_N6_QBC_AD4P_73_K19
IO_L10N_T1U_N7_QBC_AD4N_73_J19
IO_L11P_T1U_N8_GC_73_J17
IO_L11N_T1U_N9_GC_73_H17
IO_L12P_T1U_N10_GC_73_H19
IO_L12N_T1U_N11_GC_73_H18
IO_L13P_T2L_N0_GC_QBC_73_G18
IO_L13N_T2L_N1_GC_QBC_73_G17
IO_L14P_T2L_N2_GC_73_F19
IO_L14N_T2L_N3_GC_73_F18
IO_L15P_T2L_N4_AD11P_73_E19
IO_L15N_T2L_N5_AD11N_73_E18
IO_L16P_T2U_N6_QBC_AD3P_73_F16
IO_L16N_T2U_N7_QBC_AD3N_73_E16
IO_L17P_T2U_N8_AD10P_73_G20
IO_L17N_T2U_N9_AD10N_73_F20
IO_L18P_T2U_N10_AD2P_73_E17
IO_L18N_T2U_N11_AD2N_73_D16
IO_T2U_N12_73_G16
IO_T3U_N12_73_A20
IO_L19P_T3L_N0_DBC_AD9P_73_B18
IO_L19N_T3L_N1_DBC_AD9N_73_B17
IO_L20P_T3L_N2_AD1P_73_D17
IO_L20N_T3L_N3_AD1N_73_C17
IO_L21P_T3L_N4_AD8P_73_C19
IO_L21N_T3L_N5_AD8N_73_C18
IO_L22P_T3U_N6_DBC_AD0P_73_A19
IO_L22N_T3U_N7_DBC_AD0N_73_A18
IO_L23P_T3U_N8_73_D20
IO_L23N_T3U_N9_73_D19
IO_L24P_T3U_N10_73_C20
IO_L24N_T3U_N11_73_B20
XCVU9PFLGA2104
BANK 73
U1
B20
C20
SOC_2104_1MM_IRON
SOC_VU9P_FLGA2104_IRONWOOD
L18
A19
G17
J19
A20
G16
F18
E16
D17
F20
G20
F16
E18
C19
E19
C18
B17
D16
E17
C17
D19
D20
G18
H19
K19
A18
K18
F19
H18
H17
J17
B18
N17
G19
P16
P19
J16
N19
K17
P17
K16
L19
T18
M17
R18
T19
M18
D18
L17
N18
L16
R19
A17
R17
P18
M16
H16
GND
1/10W
240
R1071
2
1
1%
VCC1V2_FPGA VCC1V2_FPGA
GPIO_DIP_SW3
CPU_RESET
GPIO_DIP_SW1 DDR4_C1_DQ64
DDR4_C1_DQ65
DDR4_C1_DQ66
DDR4_C1_DQ67
DDR4_C1_DQ68
DDR4_C1_DQ69
DDR4_C1_DQ70
DDR4_C1_DQ71
DDR4_C1_DQS8_T
DDR4_C1_DQS8_C
DDR4_C1_DM8
DDR4_C1_DQ14
DDR4_C1_DQ11
DDR4_C1_DQ13
DDR4_C1_DQ10
DDR4_C1_DQ9
DDR4_C1_DQ12
DDR4_C1_DQ15
DDR4_C1_RESET_B
DDR4_C1_DQ8
DDR4_C1_ALERT_B
DDR4_C1_TEN
DDR4_C1_DQS1_C
DDR4_C1_DQS1_T
DDR4_C1_DQ16
DDR4_C1_DQ18
DDR4_C1_DQ20
DDR4_C1_DQ21
DDR4_C1_DQ41
DDR4_C1_DQ42
DDR4_C1_DQ43
DDR4_C1_DQ44
DDR4_C1_DQS4_T
DDR4_C1_DQS4_C
DDR4_C1_DM5
DDR4_C1_DQ48
DDR4_C1_DQ49
DDR4_C1_DQ50
DDR4_C1_DQ51
DDR4_C1_DQ52
DDR4_C1_DQ53
DDR4_C1_DQ54
DDR4_C1_DQ55
DDR4_C1_DQ56
DDR4_C1_DQ57
DDR4_C1_DQ58
DDR4_C1_DQ59
DDR4_C1_DQ60
DDR4_C1_DQ61
DDR4_C1_DQ63
DDR4_C1_DQS6_T
DDR4_C1_DQS6_C
DDR4_C1_DQS7_T
DDR4_C1_DQS7_C
DDR4_C1_DM6
DDR4_C1_DM7
DDR4_C1_DQ38
DDR4_C1_DQ39
DDR4_C1_DQ35
DDR4_C1_DQ37
DDR4_C1_DQS5_C
DDR4_C1_DQS5_T
DDR4_C1_DQ33
DDR4_C1_DM4
DDR4_C1_DQ32
DDR4_C1_DQ34
DDR4_C1_DQ36
SI5328_INT_ALM_LS
DDR4_C1_DQ46
DDR4_C1_DQ45
DDR4_C1_DQ40
DDR4_C1_DQ47
DDR4_C1_DQ62
GPIO_DIP_SW2
DDR4_C1_DQ30
DDR4_C1_DQ27
DDR4_C1_DQ29
DDR4_C1_DQ24
DDR4_C1_DQ26
DDR4_C1_DQ25
DDR4_C1_DQ28
DDR4_C1_DQ31
DDR4_C1_DM3
DDR4_C1_DQS3_C
DDR4_C1_DQS3_T
DDR4_C1_DQ17
DDR4_C1_DQ22
DDR4_C1_DQ19
DDR4_C1_DQ23
DDR4_C1_DQS2_C
DDR4_C1_DQS2_T
GPIO_DIP_SW4
NC
NC
NC
NC
NC
NC
NC
VRP_72
VRP_72
DDR4_C1_DM1
DDR4_C1_DM2
VRP_73
VRP_73
Bank 72 HPBank 73 HP
FPGA Banks 73 72 C1 DDR4 Data
![](https://csdnimg.cn/release/download_crawler_static/88026351/bg5.jpg)
GND
1%
2
1.00K
1
R23 R24
1.00K
1%
12
2 1
1.00K
1%
R25
1.00K
1%
R42
12
VCCO_71_G9
VCCO_71_F12
VCCO_71_E15
VCCO_71_C11
VCCO_71_B14
VCCO_71_A7
VREF_71_J15
IO_L1P_T0L_N0_DBC_71_G11
IO_L1N_T0L_N1_DBC_71_G10
IO_L2P_T0L_N2_71_F11
IO_L2N_T0L_N3_71_E11
IO_L3P_T0L_N4_AD15P_71_F10
IO_L3N_T0L_N5_AD15N_71_F9
IO_L4P_T0U_N6_DBC_AD7P_71_D11
IO_L4N_T0U_N7_DBC_AD7N_71_D10
IO_L5P_T0U_N8_AD14P_71_H12
IO_L5N_T0U_N9_AD14N_71_G12
IO_L6P_T0U_N10_AD6P_71_E9
IO_L6N_T0U_N11_AD6N_71_D9
IO_T0U_N12_VRP_71_D8
IO_T1U_N12_71_A10
IO_L7P_T1L_N0_QBC_AD13P_71_C9
IO_L7N_T1L_N1_QBC_AD13N_71_C8
IO_L8P_T1L_N2_AD5P_71_D7
IO_L8N_T1L_N3_AD5N_71_C7
IO_L9P_T1L_N4_AD12P_71_B8
IO_L9N_T1L_N5_AD12N_71_B7
IO_L10P_T1U_N6_QBC_AD4P_71_A9
IO_L10N_T1U_N7_QBC_AD4N_71_A8
IO_L11P_T1U_N8_GC_71_C10
IO_L11N_T1U_N9_GC_71_B10
IO_L12P_T1U_N10_GC_71_B11
IO_L12N_T1U_N11_GC_71_A11
IO_L13P_T2L_N0_GC_QBC_71_E12
IO_L13N_T2L_N1_GC_QBC_71_D12
IO_L14P_T2L_N2_GC_71_F13
IO_L14N_T2L_N3_GC_71_E13
IO_L15P_T2L_N4_AD11P_71_H13
IO_L15N_T2L_N5_AD11N_71_G13
IO_L16P_T2U_N6_QBC_AD3P_71_F14
IO_L16N_T2U_N7_QBC_AD3N_71_E14
IO_L17P_T2U_N8_AD10P_71_G15
IO_L17N_T2U_N9_AD10N_71_F15
IO_L18P_T2U_N10_AD2P_71_H15
IO_L18N_T2U_N11_AD2N_71_H14
IO_T2U_N12_71_D15
IO_T3U_N12_71_D14
IO_L19P_T3L_N0_DBC_AD9P_71_C13
IO_L19N_T3L_N1_DBC_AD9N_71_B13
IO_L20P_T3L_N2_AD1P_71_C12
IO_L20N_T3L_N3_AD1N_71_B12
IO_L21P_T3L_N4_AD8P_71_A16
IO_L21N_T3L_N5_AD8N_71_A15
IO_L22P_T3U_N6_DBC_AD0P_71_A14
IO_L22N_T3U_N7_DBC_AD0N_71_A13
IO_L23P_T3U_N8_71_C15
IO_L23N_T3U_N9_71_C14
IO_L24P_T3U_N10_71_B16
IO_L24N_T3U_N11_71_B15
XCVU9PFLGA2104
BANK 71
SOC_2104_1MM_IRON
SOC_VU9P_FLGA2104_IRONWOOD
B16
C14
C15
A13
B15
A14
A15
U1
D15
B13
F13
A8
A9
A10
F14
G15
A16
A11
H15
B11
C7
C8
D12
F15
E14
D14
E13
B10
E12
B7
B8
D7
H13
H14
C10
C9
C12
B12
C13
G13
G12
C11
H12
E9
G10
D8
D11
F10
D9
F9
F11
J15
G11
B14
A7
E15
F12
G9
E11
D10
GND
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE:
FPGA Bank 71 C1 DDR4 Addr Ctrl
SCHEM, ROHS COMPLIANT
TEST P/N: TSS0185
5
PCB P/N: 1280906
HW-U1-VCU118_REV2_0 SCH P/N: 0381739
ASSY P/N: 0432092
76
2.0
DN
15/07/2017:01:45
03
VCC1V2_FPGA
1%
240
1
R1072
1/10W
2
R692
100
1%
2
1/10W
1
VCC1V2_FPGA
DDR4_C1_DQ1
DDR4_C1_DQ6
DDR4_C1_DQ3
DDR4_C1_DQ7
DDR4_C1_DM0
DDR4_C1_DQ0
DDR4_C1_DQ5
DDR4_C1_DQ2
DDR4_C1_DQ4
DDR4_C1_CKE
DDR4_C1_A0
DDR4_C1_A1
DDR4_C1_A2
DDR4_C1_A3
DDR4_C1_A4
DDR4_C1_A5
DDR4_C1_A6
DDR4_C1_A7
DDR4_C1_A8
DDR4_C1_A9
DDR4_C1_A10
DDR4_C1_A11
DDR4_C1_A12
DDR4_C1_A13
DDR4_C1_BA0
DDR4_C1_BA1
DDR4_C1_ODT
DDR4_C1_CS_B
DDR4_C1_BG0
DDR4_C1_ACT_B
DDR4_C1_PAR
DDR4_C1_A14_WE_B
DDR4_C1_A16_RAS_B
DDR4_C1_A15_CAS_B
DDR4_C1_CK_T
DDR4_C1_CK_C
DDR4_C1_DQS0_T
DDR4_C1_DQS0_C
DDR4_C1_DQ72
DDR4_C1_DQ73
DDR4_C1_DQ74
DDR4_C1_DQ75
DDR4_C1_DQ76
DDR4_C1_DQ77
DDR4_C1_DQ78
DDR4_C1_DQ79
DDR4_C1_DQS9_T
DDR4_C1_DQS9_C
DDR4_C1_DM9
250MHZ_CLK1_N250MHZ_CLK1_N
250MHZ_CLK1_P 250MHZ_CLK1_P
NC
VRP_71
VRP_71
Bank 71 HP
NETWORK TO BE PLACED
AND BIAS RESISTOR
TERMINATION RESISTOR
IN "FLY-BY" CONFIGURATION
PCB LAYOUT DIRECTIVE:
FPGA Bank 71 C1 DDR4 Addr Ctrl
剩余75页未读,继续阅读
资源评论
![avatar-default](https://csdnimg.cn/release/downloadcmsfe/public/img/lazyLogo2.1882d7f4.png)
![avatar](https://profile-avatar.csdnimg.cn/770baca97cdd45dfa0094e868894690c_liang_20120830.jpg!1)
littlevvip
- 粉丝: 4
- 资源: 9
上传资源 快速赚钱
我的内容管理 展开
我的资源 快来上传第一个资源
我的收益
登录查看自己的收益我的积分 登录查看自己的积分
我的C币 登录后查看C币余额
我的收藏
我的下载
下载帮助
![voice](https://csdnimg.cn/release/downloadcmsfe/public/img/voice.245cc511.png)
![center-task](https://csdnimg.cn/release/downloadcmsfe/public/img/center-task.c2eda91a.png)
安全验证
文档复制为VIP权益,开通VIP直接复制
![dialog-icon](https://csdnimg.cn/release/downloadcmsfe/public/img/green-success.6a4acb44.png)