Application Report
SLAA469–September 2010
Audio Serial Interface Configurations for Audio Codecs
Jorge Arbona, Uttam Agarwal........................................................................... Audio Converter Products
ABSTRACT
An audio serial interface (ASI) provides a means to transfer non-buffered audio data between processors
and/or audio converters. These data are typically encoded in PCM twos complement format, although
other format variations may be possible to achieve companding for lower data rate transfers. Audio
converters based on the delta-sigma (ΔΣ) architecture require an internal master clock that operates at a
much faster rate than the target sample rate. Although there are several means to obtain this master
clock, care must be taken to ensure that this clock does not drift with respect to the ASI. This report
discusses several configurations that prevent such situations.
Contents
1 Introduction .................................................................................................................. 1
2 ASI Configurations .......................................................................................................... 2
List of Figures
1 Repeated Sample (Master Clock Slower than Ideal)................................................................... 2
2 ASI Slave Mode ............................................................................................................. 3
3 ASI Slave Mode (Independent Master Clock)........................................................................... 4
4 ASI Slave Mode (Generating Master Clock from BCLK) .............................................................. 4
5 ASI Master Mode ........................................................................................................... 5
1 Introduction
Each system has different requirements when it comes to interfacing to an audio codec ASI. The most
common configurations are the master and slave modes. When the audio codec ASI is configured in
master mode, its bit clock (BCLK) and word clock (WCLK) pins are output. In slave mode, BCLK and
WCLK are inputs to the codec ASI. This relationship might seem straightforward. However, care must be
taken when the ASI is configured in slave mode to ensure that the oversampled data that are decimated
always fall within the correct target rate time slot.
If a master clock is a free-running clock and it is fed to a converter, it will not be frequency-locked to the
frame clock (WCLK) of an independent ASI. Any deviation from the ideal will eventually result in a skipped
or repeated sample (assuming that the architecture repeats samples). For example, if a host processor
provides an ideal 48-kHz WCLK with respect to absolute time, its respective ideal master clock could be
exactly (128 ● WCLK) = 6.144 MHz. If a master clock from a non-ideal crystal is provided directly to the
converter modulator with a 0.001% error, this clock could result in 6.14393856 MHz. Eventually this slower
clock will result in a repeated sample out of the ASI bus. Of course, there is no such thing as an ideal
master or ASI clocks.
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SLAA469–September 2010 Audio Serial Interface Configurations for Audio Codecs
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