OpenCores USB Function Core January 27, 2002
www.opencores.org Rev. 1.5 1 of 63
Revision History
Rev. Date Author Description
0.1 6/1/01 Rudolf
Usselmann
First Draft
0.4 10/1/01 RU Dropped the linked list for endpoints idea, removed the buffer.
shared bit, added and modified registers.
Added Appendix B: Configuring the Core.
0.5 11/1/01 RU Changed buffer memory to a dual ported SSRAM.
Added quadruple buffering.
Filled in CSR register.
Added size field to end point buffers.
0.6 13/1/01 RU Added Change bars.
Changed buffer memory back to single port SSRAM.
Removed quadruple buffering (back to double buffering).
Enhanced the way buffers work, added description.
Added data organization section.
Added various references to latency and bandwidth requirements.
Added USB core behavior section.
0.7 15/1/01 RU Added frame number and time (FRM_NAT) register.
Filled in USB core behavior section.
Filled in most of the flowcharts.
Fixed endpoint interrupt register.
Added suspend output to wishbone IF.
Added names to some of the bits in the endpoint registers.
0.8 20/1/01 RU Changed document format to double sided.
Added Suspend and Resume Interrupts.
Added RX control of packet that are not MAX_PL_SZ.
Added vendor control IO port register and IOs.
Added Setup description.
0.9 31/1/01 RU Added DMA operations and signals.
Added separate core selects for registers and buffer memory.
0.9b 20/2/01 RU Some minor typing fixes.
Added a brief discussion about PID sequencing.
Modified the interrupts.
Modified the WISHBONE interface.
1.0 28/2/01 RU Added Buffer Overflow & Underflow descriptions.
Changed clock domain separation (Figure 1).
Removed document status “Preliminary Draft”.
1.1 7/3/01 RU Added USB device control flow charts.
Gave Names to Endpoint Registers.
Added Interrupt Section.
Added Suspend & Resume Section.
Added Appendix C: USB Core Structure.
Made various grammar and syntax corrections.
