################################################################################
# Vivado (TM) v2016.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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matlab-vivado2019.2平台下通过verilog实现图像的sobel边缘提取-源码 (332个子文件)
__synthesis_is_complete__ 0B
xsim.ini.bak 27KB
elaborate.bat 1KB
compile.bat 966B
simulate.bat 878B
compile.bat 453B
elaborate.bat 426B
simulate.bat 261B
runme.bat 229B
runme.bat 229B
blurred_lena.bmp 257KB
blurred_lena.bmp 257KB
blurred_lena.bmp 257KB
wild_gray.bmp 257KB
xsim_1.c 19KB
xsim.dbg 24KB
xsim.dbg 23KB
imageProcessTop.dcp 334KB
outputBuffer.dcp 79KB
outputBuffer.dcp 79KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
simulate.do 355B
simulate.do 355B
simulate.do 343B
elaborate.do 215B
simulate.do 201B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 336KB
xsimk.exe 225KB
run.f 1KB
usage_statistics_ext_xsim.html 3KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
.xsim_webtallk.info 64B
xsim.ini 27KB
xsim.ini 114B
xsim.ini 114B
webtalk_14640.backup.jou 1KB
webtalk.jou 1KB
vivado.jou 1KB
webtalk.jou 973B
webtalk_1699608.backup.jou 973B
vivado.jou 883B
vivado.jou 804B
ISEWrap.js 8KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
simulate.log 40.67MB
runme.log 179KB
runme.log 38KB
vivado.log 37KB
compile.log 10KB
xvlog.log 8KB
elaborate.log 3KB
elaborate.log 2KB
xvhdl.log 2KB
webtalk_1699608.backup.log 1KB
webtalk.log 1KB
xvlog.log 1KB
xsimcrash.log 1KB
webtalk_14640.backup.log 1KB
webtalk.log 1KB
xsimkernel.log 316B
xsimkernel.log 211B
simulate.log 50B
xsimcrash.log 0B
xvhdl.log 0B
Convolution.lpr 290B
xsim.mem 35KB
xsim.mem 33KB
xsim_0.win64.obj 188KB
xsim_1.win64.obj 14KB
elab.opt 220B
vivado.pb 273KB
vivado.pb 63KB
xvlog.pb 13KB
xelab.pb 4KB
xelab.pb 4KB
xvhdl.pb 3KB
xvlog.pb 2KB
imageProcessTop_utilization_synth.pb 226B
outputBuffer_utilization_synth.pb 213B
xvhdl.pb 16B
tb_vlog.prj 2KB
vlog.prj 1022B
tb_vlog.prj 806B
tb_vhdl.prj 270B
tb_vhdl.prj 215B
vhdl.prj 179B
xsim.reloc 38KB
xsim.reloc 37KB
xil_defaultlib.rlx 2KB
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