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ARM926EJ-S Technical Reference Manual Copyright © 2001-2008 ARM Limited. All rights reserved. Release Information The following changes have been made to this book.
Web Address http://www.arm.com ARM DDI 0198E Copyright C 2001-2008 ARM Limited. All rights reserved Copyright C 2001-2008 ARM Limited. All rights reserved ARM DDI 0198E Contents ARM926EJ-S Technical Reference Manual Preface about this manual XVIll Feedback……xxi Chapter 1 Introduction 1.1 About the aRM926EJ-s processor 1-2 Chapter 2 Programmers Model 2.1 About the programmer's model ∴2-2 2.2 Summary of ARM926EJ-S system control coprocessor(CP 15) registers. 2-3 2.3 Register descriptions 2-7 Chapter 3 Memory Management Unit 3.1 about the mmu 3-2 3.2 Address translation B面面面面面面B国 3-5 3.3 MMU faults and cPu aborts 3-20 3.4 Domain access control .3-23 3.5 ault checKing sequence 3-25 3.6 External aborts 面面面面面 3-28 3.7 tLB structure 3-30 ARM DDI 0198E Copyright C 2001-2008 ARM Limited. All rights reserved Contents Chapter 4 Caches and write Buffer 4.1 about the caches and write buffer 4-2 4.2 Write buffer 4-4 4.3 Enabling the caches… 4-5 4.4 TCM and cache access priorities 4-7 4.5 Cache MVa and Set/Way formats……………..….….…........4-8 Chapter 5 Tightly-Coupled Memory Interface About the tightly-coupled memory interface 5-2 5.2 TCM interface signals 5.3 TCM interface bus cycle types and timing 5-8 5.4 TCM programmers model 5-19 5.5 TCM interface examples 5-21 5.6 TCM access penalties 5-29 5.7 TCM write buffer 5-30 5.8 Using synchronous SRAM as TCM memory……… 5-31 5.9 TCM clock gating…… 5-32 Chapter 6 Bus Interface Unit 6.1 about the bus interface unit 6-2 6.2 Supported AHb transfers 6-3 Chapter 7 Noncacheable instruction Fetches 7.1 about noncacheable instruction fetches 7-2 Chapter 8 Coprocessor Interface 8.1 About the arm926EJ-s external coprocessor interface ∴82 8.2 LDC/STC 8.3 MCR/MRC 8-6 8.4 CDP∴ 8-8 8.5 Privileged instructions 8-9 8.6 Busy-waiting and interrupts 8-10 8.7 CPBURST .8-11 8.8 CPABORT 8-12 8.9 nCPINSTRVALID 8-13 8.10 Connecting multiple external coprocessors 8-14 Chapter 9 Instruction Memory Barrier 9.1 About the instruction memory barrier operation 9-2 92 IMB operation 9.3 Example IMB sequences 9-5 Chapter 10 Embedded Trace Macrocell Support 10.1 About Embedded Trace Macrocell support 10-2 Copyright C 2001-2008 ARM Limited. All rights reserved ARM DDI 0198E Contents Chapter 11 Debug Support 11.1 About debug support 11-2 Chapter 12 Power Management 12.1 About power management ∴12-2 Appendix a Signal Descriptions A 1 Signal properties and requirements A-2 A.2 AHB related signals A-3 A.3 Coprocessor interface signals A-5 A.4 Debug signals A-7 A.5 JTAG signals A-8 A.6 Miscellaneous signals……… ∴A-9 A.7 ETM interface signals……… A-10 A.8 TCM interface signals A-12 Appendix B CP15 Test and Debug Registers B. 1 About the Test and Debug Registers B-2 Glossary ARM DDI 0198E Copyright C 2001-2008 ARM Limited. All rights reserved Contents Copyright C 2001-2008 ARM Limited. All rights reserved ARM DDI 0198E List of tables ARM926EJ-S Technical Reference Manual nge History lI Table 2-1 CP15 register summary 2-3 Table 2-2 Address types in ARM926EJ-S 2-4 Table 2-3 CP15 abbreviations 2-5 Table 2-4 Reading from register co 2-7 Table 2-5 Register0, iD code∴… 2-8 Table 2-6 Ctype encoding 2-9 Table 2-7 Cache size encoding(M=O) .2-10 Table 2-8 Cache associativity encoding(M= 2-10 Table 2-9 Line length encoding 2-10 Table 2-10 Example cache t ype register format 2-11 Table 2-11 Control bit functions register c1 2-13 Table 2-12 Effects of Control Register on caches 2-14 Table 2-13 Effects of Control Register on TCM interface 2-15 Table 2-14 Domain access control defines 2-17 Table 2-15 FSR bit field descriptions 2-18 Table 2-16 FSR status field encoding 2-19 Table 2-17 Function descriptions register c7…………….……………………………220 Table 2-18 Cache operations C7 221 Table 2-19 Register c8 TLB operations 2-24 ARM DDI 0198E Copyright C 2001-2008 ARM Limited. All rights reserved List of tables Table 2-20 Cache Lockdown Register instructions 2-26 Table 2-21 Cache Lockdown Register L bits 2-26 Table 2-22 TCM Region Register instructions .2-28 Table 2-23 TCM Region Register c9 2-29 Table 2-24 TCM Size field encoding ∴2-29 Table 2-25 Programming the tlb lockdown register 2-31 able 2-26 FCSE PID Register operations 2-33 Table 2-27 Context ID register operations 2-34 Table 3-1 MMU program-accessible CP15 registers 3-4 Table 3-2 First-level descriptor bits 3-9 Table 3-3 Interpreting first-level descriptor bits [1: 0] 3-10 Table 3-4 Section descriptor bits 3-10 Table 3-5 Coarse page table descriptor bits…… 3-11 Table 3-6 Fine page table descriptor bits 3-12 Table 3-7 Second-level descriptor bits 3-14 Table 3-8 Interpreting page table entry bits [1: 0 .3-15 Table 3-9 Priority encoding of fault status 3-21 ab|e3-10 FAR Values for multi-word transfers 3-22 Table 3-11 Domain access control register, access control bits 3-23 Table 3-12 Interpreting access permission(AP)bits 323 Table 4-1 CP15 c1 I and m bit settings for the iCache 4-5 Table 4-2 Page table C bit settings for the ICache 4-5 Table 4-3 CP15 c1 C and m bit settings for the dcache..............................4-6 Table 4-4 Page table C and b bit settings for the DCache 4-6 Table 4-5 Instruction access priorities to the tCM and cache 4-7 Table 4-6 Data access priorities to the tcm and cache 4-7 Table 4-7 Values of s and nsets 4-9 Table 5-1 Relationship between DMDMaeN, DRDMACS, and DRIDle 5-6 Table 6-1 Supported HBURST encodings Table 6-2 HPROT[3: 0] and DHPRoT[3: 0] attributes 6 Table 8-1 Handshake signal enconⅰng… 8-5 Table 8-2 CPBURST encoding 8-11 Table 11-1 Scan chain 15 format 11-2 Table 11-2 Scan chain15 mapping to CP15 registers…………………………….11-3 Table A-1 AHB related signals………….…..….….….….….….….….….…….…….….….…A3 Table a-2 Coprocessor interface signals A-5 Table A-3 Debug signals A-7 Table a-4 JTAG signals A-8 Table A-5 Miscellaneous signals A-9 able A-6 ETM interface signals…… A-10 Table A-7 TCM interface signals........ A-12 Table b-1 Debug override Register…… .B-3 Table b-2 Trace Control Register bit assignments B-5 Table b-3 MMU test operation instructions B-6 Table b-4 Encoding of the main TLB entry-select bit fields B-7 Table B-5 Encoding of the tlb mva tag bit fields B-7 Table B-6 Encoding of the TLB entry PA and aP bit fields B-8 Copyright C 2001-2008 ARM Limited. All rights reserved ARM DDI 0198E

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