ASICs...THE COURSE (1 WEEK)
1
CMOS LOGIC
• CMOS transistor (or device)
• A transistor has three terminals: gate, source, drain (and a fourth that we ignore for a
moment)
• An MOS transistor looks like a switch (conducting/on, nonconducting/off, not open or
closed)
Key concepts: The use of transistors as switches • The difference between a flip-flop and a
latch • Setup time and hold time • Pipelines and latency • The difference between datapath,
standard-cell, and gate-array logic cells • Strong and weak logic levels • Pushing bubbles •
Ratio of logic • Resistance per square of layers and their relative values in CMOS • Design
rules and λ
CMOS transistors viewed as switches • a CMOS inverter
gate
drain
source
'1'
=
'0'
=
n-channel transistor
gate
drain
source
'1'
=
'0'
=
p-channel transistor
'1'
=
'1'
=
'0'
=
'0'
=
VDDVDD
'0' '1'
'1'
'0'
GND or
VSS
'0'
'1'
'0' '1'
=
VDD
A F A F
(a) (c)(b)
off
onoff
on
GND or
VSS
GND or
VSS
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