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DSP-OmapL138( ARM9+DSP)芯片使用手册
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OMAP-L138是一款由德州仪器(TI)推出的高性能微处理器,专为嵌入式系统设计,尤其适合于数字信号处理(DSP)应用。该芯片集成了ARM926EJ-S RISC处理器和C674x DSP核,形成了一种双核SoC(System on Chip)解决方案。以下是对这款芯片主要特性的详细说明:
1. **双核心架构**:
- **ARM926EJ-S核心**:这是一款32位RISC微处理器,运行频率可达到375MHz或456MHz,支持32位和16位(Thumb)指令。它具备了Jazelle技术,能够加速Java字节码的执行,同时集成有实时调试功能(Embedded ICE-RT)。
- **C674x DSP核心**:这是一款高速浮点和固定点数字信号处理器,最高频率同样为375MHz或456MHz。C674x支持浮点运算、固定点运算,以及多种数据精度混合运算。
2. **浮点处理能力**:
- **浮点运算单元**:C674x DSP核心能支持每时钟周期进行最多4个单精度(SP)浮点加法,每两个时钟周期进行4个双精度(DP)浮点加法。
- **快速乘法操作**:包括单精度和双精度的乘法与除法,如每周期执行2个SP x SP -> SP的乘法,或者每两个周期执行2个SP x SP -> DP的乘法等。
3. **内存架构**:
- **指令缓存**:集成16KB的指令缓存,用于加快程序执行速度。
- **数据缓存**:16KB的数据缓存,优化数据访问效率。
- **RAM**:8KB的RAM用作向量表,还有64KB的ROM用于存储程序代码。
- **L1和L2缓存**:C674x具有两级缓存架构,32KB的L1P程序RAM/Cache和32KB的L1D数据RAM/Cache,以及256KB的L2统一映射RAM/Cache,提高内存访问速度。
4. **指令集和性能**:
- **C674x指令集**:扩展了C67x+和C64x+指令集,支持更高效的代码执行,包括16位紧凑型指令。
- **代码优化**:通过指令打包减少代码大小,8位溢出保护,所有指令都可条件执行。
- **硬件循环支持**:硬件级的模运算循环操作,提高循环效率。
- **异常处理**:支持错误检测和程序重定向的异常处理机制。
5. **软件支持**:
- **TI DSP BIOS**:一个实时操作系统(RTOS)框架,提供任务调度、中断管理等功能。
- **Chip Support Library和DSP Library**:提供对芯片硬件特性的编程接口,简化开发过程。
6. **其他特性**:
- **数据处理能力**:包括归一化、饱和运算、位计数等高级计算功能,支持受保护模式操作。
- **位字段操作**:允许提取、设置和清除位字段,增强了数据处理的灵活性。
对于从事OMAP-L138芯片开发的硬件工程师和嵌入式软件工程师来说,理解这些特性至关重要,因为它们决定了芯片在处理复杂算法和实时应用时的性能表现。在实际应用中,开发者需要结合其强大的处理能力,以及TI提供的软件工具和库,来实现高效且可靠的系统设计。
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OMAP-L138
SPRS586I –JUNE 2009–REVISED SEPTEMBER 2014
OMAP-L138 C6000™ DSP+ ARM
®
Processor
1 OMAP-L138 C6000 DSP+ARM Processor
1.1 Features
1
• Supports 32-Bit Integer, SP (IEEE Single
• Dual-Core SoC
Precision/32-Bit) and DP (IEEE Double
– 375- and 456-MHz ARM926EJ-S™ RISC MPU
Precision/64-Bit) Floating Point
– 375- and 456-MHz C674x Fixed- and Floating-
• Supports up to Four SP Additions Per Clock,
Point VLIW DSP
Four DP Additions Every Two Clocks
• ARM926EJ-S Core
• Supports up to Two Floating-Point (SP or
– 32- and 16-Bit ( Thumb
®
) Instructions
DP) Reciprocal Approximation (RCPxP) and
– DSP Instruction Extensions
Square-Root Reciprocal Approximation
– Single-Cycle MAC
(RSQRxP) Operations Per Cycle
– ARM Jazelle
®
Technology
– Two Multiply Functional Units:
– Embedded ICE-RT™ for Real-Time Debug
• Mixed-Precision IEEE Floating-Point Multiply
• ARM9™ Memory Architecture
Supported up to:
– 16KB of Instruction Cache
– 2 SP x SP → SP Per Clock
– 16KB of Data Cache
– 2 SP x SP → DP Every Two Clocks
– 8KB of RAM (Vector Table)
– 2 SP x DP → DP Every Three Clocks
– 64KB of ROM
– 2 DP x DP → DP Every Four Clocks
• C674x Instruction Set Features
• Fixed-Point Multiply Supports Two 32 x 32-
Bit Multiplies, Four 16 x 16-Bit Multiplies, or
– Superset of the C67x+ and C64x+ ISAs
Eight 8 x 8-Bit Multiplies per Clock Cycle,
– Up to 3648 MIPS and 2746 MFLOPS
and Complex Multiples
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
– Instruction Packing Reduces Code Size
– 8-Bit Overflow Protection
– All Instructions Conditional
– Bit-Field Extract, Set, Clear
– Hardware Support for Modulo Loop Operation
– Normalization, Saturation, Bit-Counting
– Protected Mode Operation
– Compact 16-Bit Instructions
– Exceptions Support for Error Detection and
• C674x Two-Level Cache Memory Architecture
Program Redirection
– 32KB of L1P Program RAM/Cache
• Software Support
– 32KB of L1D Data RAM/Cache
– TI DSP BIOS™
– 256KB of L2 Unified Mapped RAM/Cache
– Chip Support Library and DSP Library
– Flexible RAM/Cache Partition (L1 and L2)
• 128KB of RAM Shared Memory
• Enhanced Direct Memory Access Controller 3
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
(EDMA3):
DDR2 Interfaces)
– 2 Channel Controllers
• Two External Memory Interfaces:
– 3 Transfer Controllers
– EMIFA
– 64 Independent DMA Channels
• NOR (8- or 16-Bit-Wide Data)
– 16 Quick DMA Channels
• NAND (8- or 16-Bit-Wide Data)
– Programmable Transfer Burst Size
• 16-Bit SDRAM with 128-MB Address Space
• TMS320C674x Floating-Point VLIW DSP Core
– DDR2/Mobile DDR Memory Controller with one
– Load-Store Architecture with Nonaligned
of the following:
Support
• 16-Bit DDR2 SDRAM with 256-MB Address
– 64 General-Purpose Registers (32-Bit)
Space
– Six ALU (32- and 40-Bit) Functional Units
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OMAP-L138
SPRS586I –JUNE 2009–REVISED SEPTEMBER 2014
www.ti.com
• 16-Bit mDDR SDRAM with 256-MB Address – IEEE 802.3 Compliant
Space
– MII Media-Independent Interface
• Three Configurable 16550-Type UART Modules:
– RMII Reduced Media-Independent Interface
– With Modem Control Signals
– Management Data I/O (MDIO) Module
– 16-Byte FIFO
• Video Port Interface (VPIF):
– 16x or 13x Oversampling Option
– Two 8-Bit SD (BT.656), Single 16-Bit or Single
• LCD Controller Raw (8-, 10-, and 12-Bit) Video Capture
Channels
• Two Serial Peripheral Interfaces (SPIs) Each with
Multiple Chip Selects – Two 8-Bit SD (BT.656), Single 16-Bit Video
Display Channels
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interfaces with Secure Data I/O (SDIO) • Universal Parallel Port (uPP):
Interfaces
– High-Speed Parallel Interface to FPGAs and
• Two Master and Slave Inter-Integrated Circuits Data Converters
( I
2
C Bus™)
– Data Width on Both Channels is 8- to 16-Bit
• One Host-Port Interface (HPI) with 16-Bit-Wide Inclusive
Muxed Address and Data Bus For High Bandwidth
– Single-Data Rate or Dual-Data Rate Transfers
• Programmable Real-Time Unit Subsystem
– Supports Multiple Interfaces with START,
(PRUSS)
ENABLE, and WAIT Controls
– Two Independent Programmable Real-Time Unit
• Serial ATA (SATA) Controller:
(PRU) Cores
– Supports SATA I (1.5 Gbps) and SATA II
• 32-Bit Load-Store RISC Architecture
(3.0 Gbps)
• 4KB of Instruction RAM Per Core
– Supports All SATA Power-Management
Features
• 512 Bytes of Data RAM Per Core
– Hardware-Assisted Native Command Queueing
• PRUSS can be Disabled via Software to
(NCQ) for up to 32 Entries
Save Power
– Supports Port Multiplier and Command-Based
• Register 30 of Each PRU is Exported From
Switching
the Subsystem in Addition to the Normal R31
Output of the PRU Cores.
• Real-Time Clock (RTC) with 32-kHz Oscillator and
Separate Power Rail
– Standard Power-Management Mechanism
• Three 64-Bit General-Purpose Timers (Each
• Clock Gating
Configurable as Two 32-Bit Timers)
• Entire Subsystem Under a Single PSC Clock
• One 64-Bit General-Purpose or Watchdog Timer
Gating Domain
(Configurable as Two 32-Bit General-Purpose
– Dedicated Interrupt Controller
Timers)
– Dedicated Switched Central Resource
• Two Enhanced High-Resolution Pulse Width
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
Modulators (eHRPWMs):
• USB 2.0 OTG Port with Integrated PHY (USB0)
– Dedicated 16-Bit Time-Base Counter with
– USB 2.0 High- and Full-Speed Client
Period and Frequency Control
– USB 2.0 High-, Full-, and Low-Speed Host
– 6 Single-Edge Outputs, 6 Dual-Edge Symmetric
– End Point 0 (Control)
Outputs, or 3 Dual-Edge Asymmetric Outputs
– End Points 1,2,3,4 (Control, Bulk, Interrupt, or
– Dead-Band Generation
ISOC) RX and TX
– PWM Chopping by High-Frequency Carrier
• One Multichannel Audio Serial Port (McASP):
– Trip Zone Input
– Two Clock Zones and 16 Serial Data Pins
• Three 32-Bit Enhanced Capture (eCAP) Modules:
– Supports TDM, I2S, and Similar Formats
– Configurable as 3 Capture Inputs or 3 Auxiliary
– DIT-Capable
Pulse Width Modulator (APWM) Outputs
– FIFO Buffers for Transmit and Receive
– Single-Shot Capture of up to Four Event Time-
• Two Multichannel Buffered Serial Ports (McBSPs):
Stamps
– Supports TDM, I2S, and Similar Formats
• Packages:
– AC97 Audio Codec Interface
– 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
– Telecom Interfaces (ST-Bus, H100)
[ZCE Suffix], 0.65-mm Ball Pitch
– 128-Channel TDM
– 361-Ball Pb-Free PBGA [ZWT Suffix],
0.80-mm Ball Pitch
– FIFO Buffers for Transmit and Receive
• Commercial, Extended, or Industrial Temperature
• 10/100 Mbps Ethernet MAC (EMAC):
2 OMAP-L138 C6000 DSP+ARM Processor Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OMAP-L138
OMAP-L138
www.ti.com
SPRS586I –JUNE 2009–REVISED SEPTEMBER 2014
1.2 Applications
• Professional or Private Mobile Radio (PMR) • Biometric Identification
• Remote Radio Unit (RRU) • Machine Vision (Low-End)
• Remote Radio Head (RRH) • Smart Grid Substation Protection
• Industrial Automation • Industrial Portable Navigation Devices
• Currency Inspection
1.3 Description
The OMAP-L138 C6000 DSP+ARM processor is a low-power applications processor based on an
ARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than other
members of the TMS320C6000™ platform of DSPs.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)
to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor
performance through the maximum flexibility of a fully integrated, mixed processor solution.
The dual-core architecture of the device provides benefits of both DSP and reduced instruction set
computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an
ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM9 core has a coprocessor 15 (CP15), protection module, and data and program memory
management units (MMUs) with table look-aside buffers. The ARM9 core has separate 16-KB instruction
and 16-KB data caches. Both are 4-way associative with virtual index virtual tag (VIVT). The ARM9 core
also has 8KB of RAM (Vector Table) and 64KB of ROM.
The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-
KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The
level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and
data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
Although the DSP L2 is accessible by the ARM9 and other hosts in the system, an additional 128KB of
RAM shared memory is available for use by other hosts without affecting DSP performance.
For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property
and prevents external entities from modifying user-developed algorithms. By starting from a hardware-
based “root-of-trust”, the secure boot flow ensures a known good starting point for code execution. By
default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port
can be enabled during the secure boot process during application development. The boot modules are
encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and
authenticated when loaded during secure boot. Encryption and decryption protects the users’ IP and lets
them securely set up the system and begin device operation with known, trusted code.
Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure
Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption
scheme which not only protects the boot process but offers the ability to securely upgrade boot and
application software code. A 128-bit device-specific cipher key, known only to the device and generated
using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When
an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the
device can acquire the image through an external interface, such as Ethernet, and overwrite the existing
code. For more details on the supported security features or TI’s Basic Secure Boot, refer to the
TMS320C674x/OMAP-L1x Processor Security User’s Guide (SPRUGQ9).
Copyright © 2009–2014, Texas Instruments Incorporated OMAP-L138 C6000 DSP+ARM Processor 3
Submit Documentation Feedback
Product Folder Links: OMAP-L138
OMAP-L138
SPRS586I –JUNE 2009–REVISED SEPTEMBER 2014
www.ti.com
The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management
data input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I
2
C Bus
interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two
multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with
multiple chip selects; a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose
input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event
generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS);
two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced
capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two
external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower
memories or peripherals; and a higher speed DDR2/Mobile DDR controller.
The EMAC provides an efficient interface between the device and a network. The EMAC supports both
10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an
MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.
The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller
supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).
The uPP provides a high-speed interface to many types of data converters, FPGAs, or other parallel
devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-
data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to
provide control for a variety of data converters.
A video port interface (VPIF) is included providing a flexible video I/O port.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections in this document and
the associated peripheral reference guides.
The device has a complete set of development tools for the ARM9 and DSP. These tools include C
compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows
®
debugger
interface for visibility into source code execution.
Device Information
PART NUMBER PACKAGE BODY SIZE
OMAPL138ZCE NFBGA (361) 13,00 mm x 13,00 mm
OMAPL138ZWT NFBGA (361) 16,00 mm x 16,00 mm
4 OMAP-L138 C6000 DSP+ARM Processor Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: OMAP-L138
Switched Central Resource (SCR)
BOOT ROM
256KB L2 RAM
32KB
L1 RAM
32KB
L1 Pgm
16KB
I-Cache
16KB
D-Cache
AET
4KB ETB
C674x™
DSP CPU
ARM926EJ-S CPU
With MMU
DSP Subsystem
ARM Subsystem
JTAG Interface
System Control
Input
Clock(s)
64KB ROM
8KB RAM
(Vector Table)
Power/Sleep
Controller
Pin
Multiplexing
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer (x4)
Serial Interfaces
Audio Ports
McASP
w/FIFO
DMA
Peripherals
Display Internal Memory
LCD
Ctlr
128KB
RAM
External Memory InterfacesConnectivity
EDMA3
(x2)
Control Timers
ePWM
(x2)
eCAP
(x3)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/MDDR
Controller
RTC/
32-kHz
OSC
I C
(x2)
2
SPI
(x2)
UART
(x3)
McBSP
(x2)
Video
VPIF
Parallel Port
uPP
EMAC
10/100
(MII/RMII)
MDIO
USB1.1
OHCI Ctlr
PHY
USB2.0
OTG Ctlr
PHY
HPI
MMC/SD
(8b)
(x2)
SATA
Customizable Interface
PRU Subsystem
Memory
Protection
OMAP-L138
www.ti.com
SPRS586I –JUNE 2009–REVISED SEPTEMBER 2014
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
(1) Note: Not all peripherals are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
Copyright © 2009–2014, Texas Instruments Incorporated OMAP-L138 C6000 DSP+ARM Processor 5
Submit Documentation Feedback
Product Folder Links: OMAP-L138
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