Allwinner Technology CO., Ltd. A13
A13 User Manual V1.2
Copyright © 2013 Allwinner Technology. All Rights Reserved. 4
Jau.8, 2013
Table of Contents
Revision History .................................................................................................................................................. 1
Technical Items .................................................................................................................................................... 2
1. A13 Introduction ....................................................................................................................................... 23
1.1. Features .................................................................................................................................. 23
2. Pin Description .......................................................................................................................................... 26
2.1. Pin Placement Table ................................................................................................................. 26
2.2. Pin Detail Description .............................................................................................................. 26
3. Architecture ............................................................................................................................................... 27
3.1. Functional Block Diagram ........................................................................................................ 27
3.2. Memory Mapping .................................................................................................................... 27
4. Boot System ............................................................................................................................................... 31
4.1. Overview ................................................................................................................................ 31
4.2. Boot Diagram .......................................................................................................................... 31
5. Power Management Unit (PMU) ............................................................................................................. 32
5.1. Overview ................................................................................................................................ 32
5.2. PMU Register List ................................................................................................................... 32
5.3. PMU Register Description ........................................................................................................ 33
5.3.1. PMU DVFS Control Register 0 .................................................................................. 33
5.3.2. PMU DVFS Control Register 1(Default : 0x00001010) ............................................. 34
5.3.3. PMU DVFS Control Register 2 .................................................................................. 34
5.3.4. PMU AXI Clock Range Register0 .............................................................................. 35
5.3.5. PMU AXI Clock Range Register1 .............................................................................. 35
5.3.6. PMU DVFS Control Register 3 .................................................................................. 35
5.3.7. PMU DVFS TimeOut Control Register(Default : 0x00000027) .................................. 35
5.3.8. PMU IRQ En Register ................................................................................................ 36
5.3.9. PMU IRQ Status Register .......................................................................................... 37
5.3.10. PMU Status Register .................................................................................................. 38
5.3.11. PMU CPUVDD DCDC Control Register Address(Default : 0x00000023) ................. 38
5.3.12. PMU TWI Address(Default : 0x00000068) ................................................................. 38
5.3.13. PMU CPUVDD Value(Default : 0x00000016) ............................................................ 38
5.3.14. PMU CPUVDD Voltage Ramp Control in DVM .......................................................... 39
5.3.15. PMU 32KHz CPUVDD Minimum Value(Default : 0x0000000C) ................................ 39
5.3.16. PMU VF Table Register 0 ........................................................................................... 40
5.3.17. PMU VF Table Register 1 ........................................................................................... 40
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