1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
CPU1
01-CPU1.Sch
CPU2
02-CPU2.Sch
CPU3
03-CPU3.Sch
SDRAM
04-MEM.sch
Micro2440核心板原理图
广州友善之臂计算机科技有限公司设计出品
www.arm9.net
Schematic Diagram
Designed by Guangzhou FriendlyARM
1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
ADDR/GPA0
F7
ADDR1
E7
ADDR2
B7
ADDR3
F8
ADDR4
C7
ADDR5
D8
ADDR6
E8
ADDR7
D7
ADDR8
G8
ADDR9
B8
ADDR10
A8
ADDR11
C8
ADDR12
B9
ADDR13
H8
ADDR14
E9
ADDR15
C9
ADDR16
D9
ADDR17
G9
ADDR18
F9
ADDR19
H9
ADDR20
D10
ADDR21
C10
ADDR22
H10
ADDR23
E10
ADDR24
C11
ADDR25
G10
ADDR26
D11
AIN0
R14
AIN1
U17
AIN2
R15
AIN3
P15
AIN4/TSYM
T16
AIN5/TSYP
T17
AIN6/TSXM
R16
AIN7/TSXP
P16
Aref
U16
EXYCLK
H12
CLKOUT0/GPH9
R9
CLKOUT1/GPH10
P10
MPLLCAP
N14
UPLLCAP
P17
OM2
P13
OM3
T13
XTIpll
G14
XTOpll
G15
XTIrtc
M14
XTOrtc
L12
TOUT0/GPB0
J6
TOUT1/GPB1
J5
TOUT2/GPB2
J7
TOUT3/GPB3
K3
TCLK0/GPB4
K4
TCLK1/EINT19/GPG11
U12
DATA0
D12
DATA1
C12
DATA2
E11
DATA3
A13
DATA4
F10
DATA5
F11
DATA6
C13
DATA7
A14
DATA8
D13
DATA9
B15
DATA10
A17
DATA11
C14
DATA12
D15
DATA13
C15
DATA14
D14
DATA15
B17
DATA16
C16
DATA17
E15
DATA18
E14
DATA19
E13
DATA20
E12
DATA21
E16
DATA22
F15
DATA23
G13
DATA24
E17
DATA25
G12
DATA26
F14
DATA27
F12
DATA28
G11
DATA29
G16
DATA30
H13
DATA31
F13
nXDACK0/GPB9
L3
nXDACK1/GPB7
K7
nXDREQ0/GPB10
K6
nXDREQ1/GPB8
K5
nXBACK/GPB5
K2
nXBREQ/GPB6
L5
nGCS0
F6
nGCS1/GPA12
B2
nGCS2/GPA13
C3
nGCS3/GPA14
C4
nGCS4/GPA15
D3
nGCS5/GPA16
C2
nOE
C5
nWAIT
E4
nWE
E6
OM0
T15
OM1
R13
S3C2440
DMA Chip Select
Address
ADC Clock Timer
Data
U1A
S3C2440X
XTOrtc
XTIrtc
XTOpll
XTIpll
XTOpll
XTIpll
C6
15p
C5
15p
TSYM
C1
22p
TSYP
C2
22p
TSXM
XTIrtc
TSXP
XTOrtc
VDD33V
LADDR0
LADDR1
LADDR2
LADDR3
LADDR4
LADDR5
LADDR6
LADDR7
LADDR8
LADDR9
LADDR10
LADDR11
LADDR12
LADDR13
LADDR14
LADDR15
LADDR16
LADDR17
LADDR18
LADDR19
LADDR24
LADDR25
nXDREQ0
nXDACK0
LDATA0
LDATA1
LDATA2
LDATA3
LDATA4
LDATA5
LDATA6
LDATA7
LDATA8
LDATA9
LDATA10
LDATA11
LDATA12
LDATA13
LDATA14
LDATA15
LDATA16
LDATA17
LDATA18
LDATA19
LDATA20
LDATA21
LDATA22
LDATA23
LDATA24
LDATA25
LDATA26
LDATA27
LDATA28
LDATA29
LDATA30
LDATA31
AIN0
AIN1
AIN2
AIN3
L3MODE
L3DATA
L3CLOCK
X2
12M
nLED_1
nLED_2
nLED_3
nLED_4
CLKOUT0
CLKOUT1
X1
32.768kHz
nWAIT
LADDR20
C40
2n7
C41
680p
MPLLCAP
MPLLCAP
UPLLCAP
UPLLCAP
LnOE
LnWE
LnGCS0
LnGCS1
LnGCS2
LnGCS3
LnGCS4
LnGCS5
R68
4.7K
EINT19
VDD33V
GPB0
GPB1
R22
4.7K
VDD33V
OM0
LADDR21
LADDR22
1
2
J1
CON2
LADDR23
nRESET
RST
SW-PB
1
1
2
2
3
3
4
4
U9
MAX811
R2
470
VDD33V
C34
104
M_nRESET
板载复位电路
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