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ARM SMDK2440开发板原理图
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2009-04-24
16:12:25
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ARM SMDK2440开发板原理图 ARM SMDK2440开发板原理图
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SMDK2410 Board (S3C2410 Reference Board)
PCB Revision
Date Description
Ver : 1.0 (20020417)
April 17, 2002 First release version (Production for Customer)
Ver : 1.1 (20020509)
May 09, 2002 1. Sheet 2 (Coordinate B5) , 3 (B4) , 10 (D5) : SD card(CON11) function add CD(Card Detect) and WP(Write Protect) -> Add R169 (Unload), R170 (0), R171 (4.7K)
2. Sheet 1 (Coordinate D3, C5) , 2 (C5) : Add damping resister to SDRAM signal.(LSCLK0 10 ohm, LnWE/LnGCS6/LnSCAS/LnSRAS/LADDR2,3,4 22 ohm : R172 10 ohm , R173 ~ R179 22 ohm)
Ver : 1.2 (20020603)
June 03, 2002 1. Sheet 2 (Coordinate C5) : U1B-F14 is changed from TP2 (Probe SCLK1) to LSCLK1 signal -> Add R180 (10 ohm)
2. Sheet 4 (Coordinate C3) : U9-38 is changed from LSCLK0 signal to LSCLK1 signal
3. Sheet 8 (Coordinate A4,B4) : R167, R168 is changed from 0 ohm to 4.7K, and C187,C188 is changed from unload to 1nF.
Ver : 1.3 (20020703)
July 03, 2002 1. Sheet 2,5 (Coordinate B5,C4) : Changed, J2 2Pin ---> 3Pin
2. Sheet 10 (Coordinate D5) : Deleted, R106, R107, R109, R113 ~ R115 (0 ohm)
3. Sheet 10 (Coordinate D5) : Added, R181 ~ R186 (10Kohm)
Revision History
1.3
SMDK2410X (S3C2410X DEMO BOARD)
A3
012Monday, August 19, 2002
Title
Size Document Number Rev
Date: Sheet
of
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(Address,Data,ADC,Clock,DMA,Timmer)
NOTE!!!
Lxxxx signals should be routed as short as possible.
Ground layer is isolation Analog
(AVSS) between Digital (DVSS)
Power is isolation Analog (AVDD33V)
between Digital (VDD33V)
MCU (ADDR/DATA/ADC/CLOCK/TIMMER/INT/RESET/POWER) 1.3
SMDK2410X (S3C2410X DEMO BOARD)
A3
112Monday, August 19, 2002
SAMSUNG ELECTRONICS CO.,LTD
Title
Size Document Number Rev
Date: Sheet
of
LDATA30
LDATA24
LDATA23
LADDR1
LADDR25
LADDR21
LADDR7
LDATA28
LDATA16
LDATA8
LDATA7
LDATA2
LADDR16
LADDR0
LDATA22
LADDR22
LADDR15
LADDR8
LDATA15
LDATA13
LADDR26
LADDR18
LDATA25
LDATA18
LDATA9
LDATA1
LADDR14
LDATA21
LADDR10
LADDR3
LADDR6
LDATA29
LDATA10
LADDR12
LDATA14
LDATA12
LDATA0
LADDR19
LADDR13
LADDR9
LADDR2
LDATA31
LADDR24
LADDR17
LDATA4
LADDR5
LDATA26
LDATA3
LDATA27
LDATA20
LDATA11
LADDR20
LDATA19
LDATA17
LDATA6
LADDR23
LADDR11
LDATA5
LADDR4
LADDR[26:0]
LDATA[31:0]
nGCS4
nGCS5
nGCS2
nGCS1
nGCS0
nGCS3
OM0
OM1
LnWE
LnOEnXDREQ0
nXDREQ1
nXDACK0
nXDACK1
AIN3
AIN1
AIN6
AIN5
AIN7
Avref
AIN0
AIN4
AIN2
OM2
OM3
UPLLCAP
MPLLCAP
EXTCLK
XTIrtc
XTIpll
XTOrtc
XTOpll
KEYBOARD
nIrDATXDEN
L3MODE
L3DATA
L3CLOCK
CLKOUT0
CLKOUT1
nDIS_OFF
nSS_KBD
EINT19
nWAIT
VDDiarm VDDiarm
VDDi
VDDi
VDD33V
AVDD33V
+
C33
10uF/16V
12
C21
100nF
12
+
C31
10uF/16V
12
C19
100nF
12
R178 22
+
C32
10uF/16V
12
C22
100nF
12
+
C12
10uF/16V
12
C18
100nF
12
+
C10
10uF/16V
12
U1A
S3C2410X
U16
T15
U17
T16
R15
T17
R16
N13
N12
J11
R12
U12
P17
L13
U14
T13
H17
P16
H16
R17
F2
F1
F4
G3
G4
R11
H2
G2
H3
H4
B14
D14
A14
C13
B13
D13
A13
C12
B12
G12
D12
E12
B11
A11
C11
G11
A10
B10
E10
D10
F10
A9
D9
E9
B9
C9
E8
B8
A8
D7
E7
C7
B7
A7
C6
F7
B6
D6
A5
C5
B5
D5
A4
A3
B3
A2
A1
B2
C3
B1
C2
C1
D2
D4
D1
E3
E2
E4
E1
G1
G5
D17
E15
E16
E14
E17
F15
C16
G13
E13
R14
U15
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Vref
EXTCLK
CLKOUT0/GPH9
CLKOUT1/GPH10
MPLLCAP
UPLLCAP
OM2
OM3
XTIpll
XTIrtc
XTOpll
XTOrtc
TOUT0/GPB0
TOUT1/GPB1
TOUT2/GPB2
TOUT3/GPB3
TCLK0/GPB4
TCLK1/EINT19/GPG11
nXDACK0/GPB9
nXDACK1/GPB7
nXDREQ0/GPB10
nXDREQ1/GPB8
ADDR0/GPA0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16/GPA1
ADDR17/GPA2
ADDR18/GPA3
ADDR19/GPA4
ADDR20/GPA5
ADDR21/GPA6
ADDR22/GPA7
ADDR23/GPA8
ADDR24/GPA9
ADDR25/GPA10
ADDR26/GPA11
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA30
DATA31
nXBACK/GPB5
nXBREQ/GPB6
nGCS0
nGCS1/GPA12
nGCS2/GPA13
nGCS3/GPA14
nGCS4/GPA15
nGCS5/GPA16
nOE
nWAIT
nWE
OM0
OM1
C17
100nF
12
+
C11
10uF/16V
12
C20
100nF
12
RA1 22
1 8
2 7
3 6
4 5
+
C9
10uF/16V
12
+
C30
10uF/16V
12
C1
100nF
12
B2
INDUCTOR_0 (SMD Bead)
1 2
B1
INDUCTOR_0 (SMD Bead)
1 2
+
C35
10uF/16V
12
C4
100nF
12
+
C34
10uF/16V
12
C3
100nF
12
+
C36
10uF/16V
12
C26
100nF
12
C7
100nF
12
R179 22
C6
100nF
12
R177 22
C2
100nF
12
C5
100nF
12
+
C27
10uF/16V
12
+
C28
10uF/16V
12
+
C29
10uF/16V
12
RA2 22
1 8
2 7
3 6
4 5
C24
100nF
12
C23
100nF
12
C25
100nF
12
C8
100nF
12
+
C15
10uF/16V
12
+
C16
10uF/16V
12
R173 22
+
C14
10uF/16V
12
+
C13
10uF/16V
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(External Interrupt , Reset , Power)
NAND Flash Configuration
Address Step
J3 (NCON)
0
1
512 Byte/Page , 3 Step Addressing
512 Byte/Page , 4 Step Addressing
(nCD_SD)
MCU (LCD/JTAG/UART/USB/NAND/MMC/UART/USB/SPI/MEMORY) 1.3
SMDK2410X (S3C2410X DEMO BOARD)
A3
212Monday, August 19, 2002
SAMSUNG ELECTRONICS CO.,LTD
Title
Size Document Number Rev
Date: Sheet
of
VD4
VD0
VD9
VD1
VD23
VD12
VD21
VD20
VD22
VD15
VD6
VD14
VD7
VD17
VD2
VD16
VD8
VD13
VD3
VD19
VD11
VD10
VD18
VD5
nLED_8
IRQ_PCMCIA
nLED_1
nRESET
VDDalive
nLED_4
nLED_2
EINT0
KBDINT
IRQ_LAN
nYPON
nXPON
I2SSCLK
nSS_SPI
DP1
YMON
I2SSDO
IICSCL
XMON
DN1
IICSDA
CDCLK
DP0
I2SLRCK
DN0
I2SSDI
VD[23:0]
TMS
TXD0
TDI
RXD1
LCDVF2
TCK
VCLK
LCD_PWREN
nCTS0
RXD0
RXD2
TXD1
LCDVF0
VFRAME
nTRST
TXD2
VM
LCDVF1
nRTS0
TDO
VLINE
SDCMD
LnWBE2
nFCE
SDDATA2
LSCKE
LnWBE3
nFRE
CLE
LnWBE0
SDDATA1
LSCLK0
LnWBE1
ALE
SDCLK
nFWE
SDDATA3
SDDATA0
PWREN
EINT11
LnSRAS
LEND
DMAMODE1
SPICLK
SPIMISO
SPIMOSI
KBDSPIMISO
KBDSPIMOSI
KBDSPICLK
nIRQ_PCMCIA
DMAMODE0
DMASTART
LnSCAS
LnGCS6
EINT2
nGCS7
WP_SD
LSCLK1
RnB
VDDIO
VDDADC
VDDRTC VDDUPLL
VDDMPLL
VDDUPLL
VDDiarm
VDDi
VDDMPLL
VDDMOP
VDDADC
VDD33V
VDD33V VDD33V
R180 10
U1B
S3C2410X
L1
L2
L4
M3
M4
M2
N1
N3
N2
N4
P1
P3
P2
T1
R2
U1
T2
R3
R4
U2
T3
U3
T4
P4
J4
J2
J6
K4
K2
K6
L6
L3
A17
B16
C15
A16
F16
F17
C14
B15
D16
F13
F14
G14
H12
R13
U13
G17
G16
G15
T6
P6
R6
N7
P7
R7
H5
H6
J1
J5
J3
L14
L12
K15
K17
K16
K14
K13
K12
L16
L7
M8
T5
P5
N6
U5
U6
T7
U7
U9
R9
P8
R10
T8
L9
P9
P11
U11
T11
M11
T12
P13
N11
M10
VD0/GPC8
VD1/GPC9
VD2/GPC10
VD3/GPC11
VD4/GPC12
VD5/GPC13
VD6/GPC14
VD7/GPC15
VD8/GPD0
VD9/GPD1
VD10/GPD2
VD11/GPD3
VD12/GPD4
VD13/GPD5
VD14/GPD6
VD15/GPD7
VD16/GPD8
VD17/GPD9
VD18/GPD10
VD19/GPD11
VD20/GPD12
VD21/GPD13
VD22/nSS1/GPD14
VD23/nSS0/GPD15
LEND/GPC0
VCLK/GPC1
VLINE:HSYNC/GPC2
VFRAME:VSYNC/GPC3
VM:VDEN/GPC4
LCDVF0/GPC5
LCDVF1/GPC6
LCDVF2/GPC7
nBE0:nWBE0:DQM0
nBE1:nWBE1:DQM1
nBE2:nWBE2:DQM2
nBE3:nWBE3:DQM3
nSCS0:nGCS6
nSCS1:nGCS7
nSCAS
nSRAS
SCKE
SCLK0
SCLK1
ALE/GPA18
CLE/GPA17
R/nB
NCON
nFCE/GPA22
nFRE/GPA20
nFWE/GPA19
SDCLK/GPE5
SDCMD/GPE6
SDDATA0/GPE7
SDDATA1/GPE8
SDDATA2/GPE9
SDDATA3/GPE10
nTRST
TCK
TDI
TDO
TMS
nCTS0/GPH0
nRTS0/GPH1
TXD0/GPH2
RXD0/GPH3
TXD1/GPH4
RXD1/GPH5
nRTS1/TXD2/GPH6
nCTS1/RXD2/GPH7
UCLK/GPH8
IICSCL/GPE14
IICSDA/GPE15
I2SLRCK/GPE0
I2SSCLK/GPE1
CDCLK/GPE2
I2SSDI/nSS0/GPE3
I2SSDO/I2SSDI/GPE4
SPIMISO0/GPE11
SPIMOSI0/GPE12
SPIMISO1/EINT13/GPG5
SPIMOSI1/EINT14/GPG6
SPICLK0/GPE13
SPICLK1/EINT15/GPG7
nSS0/EINT10/GPG2
nSS1/EINT11/GPG3
LCD_PWREN/EINT12/GPG4
XMON/EINT20/GPG12
nXPON/EINT21/GPG13
YMON/EINT22/GPG14
nYPON/EINT23/GPG15
DN0
DP0
DN1/PDN0
DP1/PDP0
R175 22
TP3
PROBE UCLK
1
1
R174 22
R1
4.7K
1 2
TP1
PROBE nRSTOUT
1
1
R176 22
R2
4.7K
1 2
U1C
S3C2410X
J12
J16
N14
N17
M16
M17
M15
M14
L15
L17
R8
U8
U10
T10
P10
J17
J15
M12
P15
G6
J14
D11
C4
C17
C8
J13
P14
L11
G7
K3
L5
M7
N10
R1
N5
D8
E11
A15
A6
E5
B4
H14
K1
M6
N16
N9
T14
F6
F9
B17
F11
H15
M13
N15
H1
J7
M1
N8
M5
M9
U4
F12
E6
A12
D3
G9
F8
F3
C10
D15
F5
H13
K5
T9
P12
R5
nRESET
nRSTOUT/GPA21
EINT0/GPF0
EINT1/GPF1
EINT2/GPF2
EINT3/GPF3
EINT4/GPF4
EINT5/GPF5
EINT6/GPF6
EINT7/GPF7
EINT8/GPG0
EINT9/GPG1
EINT16/GPG8
EINT17/GPG9
EINT18/GPG10
nBATT_FLT
PWREN
RTCVDD (1.8V)
VDDA_ADC (3.3V)
VDDalive (1.8V)
VDDalive (1.8V)
VDDi (1.8V)
VDDi (1.8V)
VDDi (1.8V)
VDDi (1.8V)
VDDi (1.8V)
VDDi_MPLL (1.8V)
VDDi_UPLL (1.8V)
VDDiarm (1.8V)
VDDiarm (1.8V)
VDDiarm (1.8V)
VDDiarm (1.8V)
VDDiarm (1.8V)
VDDiarm (1.8V)
VDDiarm (1.8V)
VDDMOP (SCLK 66MHz:1.8V,85:2.5V,100:3.3V)
VDDMOP (SCLK 66MHz:1.8V,85:2.5V,100:3.3V)
VDDMOP (SCLK 66MHz:1.8V,85:2.5V,100:3.3V)
VDDMOP (SCLK 66MHz:1.8V,85:2.5V,100:3.3V)
VDDMOP (SCLK 66MHz:1.8V,85:2.5V,100:3.3V)
VDDMOP (SCLK 66MHz:1.8V,85:2.5V,100:3.3V)
VDDMOP (SCLK 66MHz:1.8V,85:2.5V,100:3.3V)
VDDOP (3.3V)
VDDOP (3.3V)
VDDOP (3.3V)
VDDOP (3.3V)
VSSA_ADC
VSSi
VSSi
VSSi
VSSi
VSSi
VSSi_MPLL
VSSi_UPLL
VSSiarm
VSSiarm
VSSiarm
VSSiarm
VSSiarm
VSSiarm
VSSiarm
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSMOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
C38
100nF
J3
12
J1
12
C37
100nF
C39
100nF
R172 10
R3
4.7K
1 2
剩余12页未读,继续阅读
资源评论
- 凌风子2012-11-10没有什么注释性文字,表示菜鸟的我没看出什么、、
- lanshishuijing2012-08-08初学者可参考看看,挺有用
king303208
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