ADI公司的AD719x的linux驱动

/* * AD7190 AD7192 AD7195 SPI ADC driver * * Modified by wangwen base on 2011 Analog Devices Inc. * * Licensed under the GPL-2. */ #include <linux/errno.h> #include <linux/kernel.h> #include <linux/cdev.h> #include <linux/wait.h> #include <linux/init.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/spi/spi.h> #include <linux/spi/ad7192.h> #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/workqueue.h> #include <linux/sysfs.h> #include <linux/gpio.h> #include <linux/fs.h> #include <linux/sched.h> #include <linux/err.h> #include <linux/device.h> #include <linux/ioctl.h> #include <linux/delay.h> #include <mach/hardware.h> #include <mach/regs-gpio.h> #include <asm/uaccess.h> #include <asm/delay.h> /* Registers */ #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 24-bit)*/ #define AD7192_REG_FULLSALE 7 /* Full-Scale Register (RW, 24-bit)*/ /* Communications Register Bit Designations (AD7192_REG_COMM) */ #define AD7192_COMM_WEN (1 << 7) /* Write Enable */ #define AD7192_COMM_WRITE (0 << 6) /* Write Operation */ #define AD7192_COMM_READ (1 << 6) /* Read Operation */ #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ #define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */ /* Status Register Bit Designations (AD7192_REG_STAT) */ #define AD7192_STAT_RDY (1 << 7) /* Ready */ #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */ #define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */ #define AD7192_STAT_PARITY (1 << 4) /* Parity */ #define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */ #define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */ #define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */ /* Mode Register Bit Designations (AD7192_REG_MODE) */ #define AD7192_MODE_OP(x) (((x) & 0x7) << 21) /* Operation Mode Select */ #define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */ #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */ #define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/ #define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */ #define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/ #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */ #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */ #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ /* Mode Register: AD7192_MODE_SEL options */ #define AD7192_MODE_OP_CONT 0 /* Continuous Conversion Mode */ #define AD7192_MODE_OP_SINGLE 1 /* Single Conversion Mode */ #define AD7192_MODE_OP_IDLE 2 /* Idle Mode */ #define AD7192_MODE_OP_PWRDN 3 /* Power-Down Mode */ #define AD7192_MODE_OP_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ #define AD7192_MODE_OP_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ #define AD7192_MODE_OP_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ #define AD7192_MODE_OP_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ /* Mode Register: AD7192_MODE_CLKSRC options */ #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock */ #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ #define AD7192_CLK_INT 2 /* Internal 4.92 MHz MCLK2=not use */ #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz,MCLK2=out clock*/ /* Configuration Register Bit Designations (AD7192_REG_CONF) */ #define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */ #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */ #define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */ #define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */ #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */ #define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */ #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */ #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */ #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */ #define AD7192_CH_TEMP 2 /* Temp Sensor */ #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */ #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */ #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */ #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */ #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */ /* ID Register Bit Designations (AD7192_REG_ID) */ #define ID_AD7190 0x4 #define ID_AD7192 0x0 #define ID_AD7195 0x6 #define AD7192_ID_MASK 0x0F /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ #define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */ #define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */ #define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */ #define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */ #define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */ #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */ #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */ #define AD7192_INT_FREQ_MHz 4915200 #define AD7192_IOC_MAGIC 'g' #define AD7192_IOC_RD_MODE _IOR(AD7192_IOC_MAGIC,1,__u32) #define AD7192_IOC_RD_CONF _IOR(AD7192_IOC_MAGIC,2,__u32) #define AD7192_IOC_SET_RATE _IOW(AD7192_IOC_MAGIC,3,__u32) #define AD7192_IOC_SET_GAIN _IOW(AD7192_IOC_MAGIC,4,__u32) #define AD7192_IOC_SET_CHAN _IOW(AD7192_IOC_MAGIC,5,__u32) #define AD7192_IOC_RESET _IO(AD7192_IOC_MAGIC,6) #define AD7192_IOC_START_CONT _IO(AD7192_IOC_MAGIC,7) #define AD7192_IOC_START_ONESHOT _IO(AD7192_IOC_MAGIC,8) /* NOTE: * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. * The DOUT/RDY output must also be wired to an interrupt capable GPIO. */ struct ad7192_state { struct spi_device *spi; struct ad7192_platform_data *pdata; struct mutex access_lock; struct mutex op_lock; /* cdev related */ struct cdev cdev; dev_t devt; /* indicate the DRY pin*/ wait_queue_head_t ready; bool done; /* update new val,indicate new val can be read*/ struct work_struct work; wait_queue_head_t new_data_avail; bool new; unsigned int data_val; /* state of chip */ bool irq_dis; unsigned short vref_mv; unsigned int mclk; unsigned int f_order; unsigned int mode; unsigned int conf; unsigned int irq_pin; unsigned char data[4]; unsigned char devid; }; static struct class *ad719x_class; /* * raw write ad7192 reg function */ static int ad7192_write_reg(struct ad7192_state *st,unsigned char reg, unsigned size, unsigned val) { u8 *data = st->data; struct spi_transfer t = { .tx_buf = data, .len = size + 1, .cs_change = 0, }; struct spi_message m; data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg); switch (size) { case 3: data[1] = val >> 16; data[2] = val >> 8; data[3] = val; break; case 2: data[1] = val >> 8; data[2] = val; break; case 1: data[1] = val; break; default: return -EINVAL; } spi_message_init(&m); spi_message_add_tail(&t, &m); return spi_sync(st->spi, &m); } /* * raw read ad7192 reg function */ static int ad7192_read_reg(struct ad7192_state *st,unsigned char reg, unsigned *val, unsigned size) { u8 *data = st->data; int ret; struct spi_transfer t[] = { { .tx_buf = data, .len = 1, }, { .rx_buf = data, .len = size, .cs_change = 0, }, }; struct spi_message m; data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR