AT89C51 全英文说明书

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of

Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is

manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the

industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with

Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly

flexible and cost effective solution to many embedded control applications.

• 128 x 8-Bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-Bit Timer/Counters

• Six Interrupt Sources

• Programmable Serial Channel

• Low Power Idle and Power Down Modes

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32

I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial

port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for

operation down to zero frequency and supports two software selectable power saving modes. The Idle

Pin Description:

VCC Supply voltage.

GND Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL

inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.

Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to

external program and data memory. In this mode P0 has internal pullups.

Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during

program verification. External pullups are required during program verification.

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal

pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and

during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this

application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming

and verification.

Port 3 also receives

some control signals for

Flash programming and

verification.

RST

Reset input. A high on

cycles while the oscillator is

running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to

external memory. This pin is also the program pulse input (PROG) during Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be

used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during

each access to external Data Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,

ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.

Port pin

alternate functions

P3.5

t1 (timer1 external input)

P3.6

^WR (external data memory write strobe)

P3.7

^rd (external data memory read strobe)