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DG-10141-001_v1.2 | February 2022
NVIDIA Jetson TX2 NX
Product Design Guide

NVIDIA Jetson TX2 NX DG-10141-001_v1.2 | ii
Document History
DG-10141-001_v1.2
Version Date Description of Change
1.0 February 24, 2021 Initial Release
1.1 September 28, 2021 • Removed mention of interfaces for WiFi/BT in Table 2-1
“Jetson TX2 NX Interfaces”
• Updated Usage/Descriptions for PMIC_BBAT,
SHUTDOWN_REQ*, POWER_EN, SYS_RESET* and
MOD_SLEEP* in Table 5-1 “Jetson TX2 NX Power and
System Pin Descriptions”
• Updated SHUTDOWN_REQ* pull-up and MOD_SLEEP*
usage in Figure 5-1 “Jetson TX2 NX Power and Control
Block Diagram”
• Replaced much of the existing text with more detail per
power handshake signals in Section 5.1.1 “Power
Handshake Signals”
• Updated to include timing relationships in Figure 5-3
“Power Up Sequence (No Power Button – Auto-Power-
On)”
• Added sequence in Figure 5-4 “Power-up Sequence
(With Power Button)”
• Updated to include timing relationships in Figure 5-5
“Power Down – Initiated by SHUTDOWN_REQ*
Assertion”
• Updated to move GPIO00 to load switch and USB VBUS
Detect to available GPIO in Figure 6-1 “USB Connection
Example”
• Added box and note reference related to AC Caps on
Tegra RX lines in Figure 6-7 “Example PCIe
Connections”
1.2 February 25, 2022 General
•
Updated Pinout Matrix table to correct several PCIe
related pin names.
• Added USB SS and Wireless Coexistence section
• Added test points for high-speed interfaces section
Power
• Updated power control signal descriptions for
SHUTDOWN_REQ* and POWER_EN
• Added delay requirement between VDD_IN and
POWER_EN
• Updated power sequence figures

NVIDIA Jetson TX2 NX DG-10141-001_v1.2 | iii
Table of Contents
Chapter 1. Introduction ........................................................................................... 1
1.1 References .......................................................................................................................... 1
1.2 Abbreviations and Definitions ............................................................................................ 2
Chapter 2. Jetson TX2 NX ....................................................................................... 4
Chapter 3. Developer Kit Feature Considerations .................................................. 8
3.1 Button Power MCU ............................................................................................................. 8
3.2 USB SuperSpeed Hub ........................................................................................................ 9
3.3 Power over Ethernet .......................................................................................................... 9
3.4 TI TXB0108 Level Shifters .................................................................................................. 9
3.5 Features Not to be Implemented ...................................................................................... 9
Chapter 4. Module Connector ............................................................................... 10
4.1 Module Connector Details ............................................................................................... 10
4.2 Module to Mounting Hardware ........................................................................................ 10
4.3 Module Installation and Removal .................................................................................... 11
Chapter 5. Power .................................................................................................. 12
5.1 Power Supply and Sequencing ........................................................................................ 13
5.1.1 Power Handshake Signals ......................................................................................... 13
5.1.2 Power Sequencing ..................................................................................................... 15
Chapter 6. USB and PCI Express .......................................................................... 17
6.1 USB ................................................................................................................................... 19
6.1.1 USB 2.0 Design Guidelines ........................................................................................ 20
6.1.2 USB 3.0 Design Guidelines ........................................................................................ 20
6.1.3 Common USB Routing Guidelines ............................................................................ 23
6.2 PCIe ................................................................................................................................... 24
6.2.1 PCIe Design Guidelines ............................................................................................. 26
6.3 Gigabit Ethernet ............................................................................................................... 28
Chapter 7. Display ................................................................................................. 31
7.1 MIPI DSI ............................................................................................................................ 31
7.1.1 MIPI DSI and CSI Design Guidelines ......................................................................... 32
7.1.2 MIPI DSI and CSI Connection Guidelines .................................................................. 33
7.2 HDMI, eDP, and DP .......................................................................................................... 33
7.2.1 eDP and DP ................................................................................................................ 34
7.2.1.1 eDP and DP Routing Guidelines ......................................................................... 35
7.2.2 HDMI ........................................................................................................................... 39
7.2.2.1 HDMI Routing Guidelines ................................................................................... 40

NVIDIA Jetson TX2 NX DG-10141-001_v1.2 | iv
Chapter 8. MIPI CSI Video Input ............................................................................ 47
8.1 CSI Design Guidelines ...................................................................................................... 51
Chapter 9. SD Card and SDIO ............................................................................... 52
Chapter 10. Audio ................................................................................................... 55
Chapter 11. Miscellaneous Interfaces .................................................................... 58
11.1 I2C ................................................................................................................................. 58
11.1.1 I2C Design Guidelines ................................................................................................ 59
11.2 SPI ................................................................................................................................. 61
11.2.1 SPI Design Guidelines ................................................................................................ 62
11.3 CAN ................................................................................................................................. 63
11.4 Fan ................................................................................................................................. 63
11.5 UART ................................................................................................................................. 64
11.6 Debug ................................................................................................................................ 65
11.6.1 Debug UART ............................................................................................................... 66
Chapter 12. PADS ................................................................................................... 67
12.1 Internal Pull-ups for Dual-Voltage Block Pins Powered at 1.8V ................................... 67
12.2 Schmitt Trigger Usage ..................................................................................................... 67
12.3 Pins Pulled and Driven High During Power-ON ............................................................. 68
Chapter 13. Unused Interface Terminations .......................................................... 70
13.1 Unused Multi-purpose Standard CMPS Pad Interfaces ................................................ 70
Chapter 14. USB SS and Wireless Coexistence ...................................................... 71
14.1 Mitigation Techniques ...................................................................................................... 71
Chapter 15. Jetson TX2 NX Pin Descriptions and Design Checklist ....................... 73
Chapter 16. General Routing Guidelines ................................................................ 74
16.1 Signal Name Conventions ................................................................................................ 74
16.2 Routing Guideline Format ................................................................................................ 75
16.3 Signal Routing Conventions ............................................................................................. 75
16.4 General Routing Guidelines ............................................................................................. 75
16.5 General PCB Routing Guidelines .................................................................................... 76
16.6 Common High-Speed Interface Requirements .............................................................. 77
16.7 Test Points for High-Speed Interfaces ............................................................................ 78

NVIDIA Jetson TX2 NX DG-10141-001_v1.2 | v
List of Figures
Figure 2-1. Jetson TX2 NX Block Diagram ............................................................................... 5
Figure 4-1. Jetson TX2 NX Module Installed in SODIMM Connector .................................... 10
Figure 4-2. Module to Connector Assembly Diagram ........................................................... 11
Figure 5-1. Jetson TX2 NX Power and Control Block Diagram ............................................ 13
Figure 5-2. System Power and Control Block Diagram ........................................................ 15
Figure 5-3. Power Up Sequence (No Power Button – Auto Power-On) ............................... 15
Figure 5-4. Power-Up Sequence (With Power Button) .......................................................... 15
Figure 5-5. Power Down – Initiated by SHUTDOWN_REQ* Assertion .................................. 16
Figure 5-6. Power Down – Sudden Power Loss .................................................................... 16
Figure 6-1. USB Connection Example .................................................................................... 19
Figure 6-2. IL/NEXT Plot ......................................................................................................... 22
Figure 6-3. Trace Spacing for TX/RX Non-Interleaving ......................................................... 22
Figure 6-4. Via Structures ....................................................................................................... 23
Figure 6-5. ESD Layout Recommendations ........................................................................... 23
Figure 6-6. Component Order ................................................................................................. 23
Figure 6-7. Example PCIe Connections .................................................................................. 25
Figure 6-8. AC Cap Voiding ..................................................................................................... 27
Figure 6-9. Jetson TX2 NX Ethernet Connections ................................................................. 29
Figure 6-10. Gigabit Ethernet Magnetics and RJ45 Connections ........................................... 29
Figure 7-1. DSI 1 x 2 Lane Connection Example .................................................................... 32
Figure 7-2. DP and eDP Connection Example on DP0 Pins .................................................. 35
Figure 7-3. eDP Differential Main Link Topology ................................................................... 35
Figure 7-4. S-parameter ......................................................................................................... 38
Figure 7-5. Via Topology #1 .................................................................................................... 38
Figure 7-6. Via Topology #2 .................................................................................................... 38
Figure 7-7. HDMI Connection Example .................................................................................. 39
Figure 7-8. HDMI CLK and Data Topology ............................................................................. 40
Figure 7-9. IL and FEXT Plot ................................................................................................... 43
Figure 7-10. TDR Plot ................................................................................................................ 43
Figure 7-11. HDMI Via Topology ............................................................................................... 44
Figure 7-12. Add-on Components – Top .................................................................................. 44
Figure 7-13. Add-on Components – Bottom ............................................................................ 44
Figure 7-14. AC Cap Void .......................................................................................................... 44
Figure 7-15. RPD, Chock, FET Placement ............................................................................... 44
Figure 7-16. ESD Footprint ....................................................................................................... 45
Figure 7-17. ESD Void ................................................................................................................ 45
Figure 7-18. SMT Pad Trace Entering ...................................................................................... 45
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