12
spring 2015 IEEE SOLID-STATE CIRCUITS MAGAZINE
A CirCuit for All SeASonS
Behzad Razavi
T
The StrongARM Latch
Digital Ob
ject Id
entifier 10.1109/MSSC.2015.2418155
Date of publication: 25 June 2015
The StrongARM latch topology finds
wide usage as a sense amplifier,
a comparator, or simply a robust
latch with high sensitivity. The term
“StrongARM” commemorates the use
of this circuit in Digital Equipment
Corporation’s StrongARM micropro-
cessor [1], but the basic structure was
originally introduced by Toshiba’s
Kobayashi et al. [2]. The StrongARM
latch has become popular for three
reasons: 1) it consumes zero static
power, 2) it directly produces rail-to-
rail outputs, and 3) its input-referred
offset arises from primarily one dif-
ferential pair. In this column, we
study the circuit and its properties.
Basic Operation
Figure 1(a) shows the original Strong-
ARM latch, reported in [2] without
M
8
and in [1] with
.M
8
The circuit
was later modified as depicted in
Figure 1(b) [3]. We first study the
latter and then point out the differ-
ences among these versions.
The latch of Figure 1(b) consists
of a clocked differential pair,
,MM –
12
two cross-coupled pairs,
MM –
34
and
,MM –
56
and four precharge switches,
.SS –
14
The circuit provides rail-to-
rail outputs at
X
and
Y
in response
to the polarity of
.
VV
12
in in
-
We
describe the operation in four phases.
In the first phase,
CK
is low;
M
1
and
M
2
are off; nodes
,P
,Q
,X
and
Y
are precharged to
;V
DD
and the circuit
reduces to that shown in Figure 2(a).
In the second phase,
CK
goes
high,
SS –
14
turn off, and
M
1
and
M
2
turn on, drawing a differential
current in proportion to
.
VV
12
in in
-
With
MM –
36
initially off, this current
flows from
C
P
and
C
Q
[Figure 2(b)],
thereby allowing
VV
PQ
-
to grow
and possibly exceed
.
VV
12
in in
-
That is, this phase can provide
voltage gain. We call this phase
the amplification mode. Since
the tail current is fairly constant
during this period, we can write
(/),
VV gVVCt
,,
PQ
mP
Q12 12in in
.
--
where
g
,m
12
denotes the small-sig-
nal transconductance of
M
1
and
,M
2
and
.CCC
,PQ
PQ
==
As
V
P
and
V
Q
fall to
,
VV
DD TH N
-
the cross-coupled NMOS transistors
turn on (third phase), allowing part
of the drain currents of
M
1
and
M
2
to
flow from
X
and
Y
[Figure 2(c)]. The
amplification mode therefore lasts
for approximately
(/)CIV
,PQ CM THN
seconds, where
I
CM
is the common-
mode (CM) current drawn from each
capacitance. The voltage gain in this
mode is roughly given by [4]
.A
I
gV
,
v
m12
CM
THN
.
(1)
The behavior of the latch in the
third phase can be analyzed with the
aid of the equivalent circuit shown
CK
CK
CK
CK CK
CK
V
DD
V
DD
V
DD
V
out
V
out
V
in1
V
in1
V
in2
V
in2
M
5
M
5
S
1
S
3
S
4
S
2
M
6
M
6
M
4
M
4
M
3
M
3
M
2
M
2
M
8
M
7
M
7
M
1
M
1
X
X
Y
Y
Q
Q
P
P
(a
)(
b)
Figure1: (a) The original and (b) modified StrongARM latch topologies.
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