80C186EB/80C188EB
Microprocessor
User’s Manual
80C186EB/80C188EB
Microprocessor
User’s Manual
February 1995
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions
of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear
in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark
or products.
*Other brands and names are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
© INTEL CORPORATION, 1995
iii
CONTENTS
CHAPTER 1
INTRODUCTION
1.1 HOW TO USE THIS MANUAL....................................................................................... 1-2
1.2 RELATED DOCUMENTS .............................................................................................. 1-3
1.3 CUSTOMER SERVICE.................................................................................................. 1-4
1.3.1 How to Use Intel's FaxBack Service .........................................................................1-5
1.3.2 How to Use Intel's Application BBS ..........................................................................1-5
1.3.3 How to Find the Latest
Ap
BUILDER Files, Hypertext Manuals, and
Data Sheets on the BBS ............................................................................................1-6
CHAPTER 2
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1 ARCHITECTURAL OVERVIEW .................................................................................... 2-1
2.1.1 Execution Unit ...........................................................................................................2-2
2.1.2 Bus Interface Unit .....................................................................................................2-3
2.1.3 General Registers .....................................................................................................2-4
2.1.4 Segment Registers ...................................................................................................2-5
2.1.5 Instruction Pointer .....................................................................................................2-6
2.1.6 Flags .........................................................................................................................2-7
2.1.7 Memory Segmentation ..............................................................................................2-8
2.1.8 Logical Addresses ...................................................................................................2-10
2.1.9 Dynamically Relocatable Code ...............................................................................2-13
2.1.10 Stack Implementation .............................................................................................2-15
2.1.11 Reserved Memory and I/O Space ...........................................................................2-15
2.2 SOFTWARE OVERVIEW............................................................................................ 2-17
2.2.1 Instruction Set .........................................................................................................2-17
2.2.1.1 Data Transfer Instructions .............................................................................2-18
2.2.1.2 Arithmetic Instructions ...................................................................................2-19
2.2.1.3 Bit Manipulation Instructions .........................................................................2-21
2.2.1.4 String Instructions ..........................................................................................2-22
2.2.1.5 Program Transfer Instructions .......................................................................2-23
2.2.1.6 Processor Control Instructions ......................................................................2-27
2.2.2 Addressing Modes ..................................................................................................2-27
2.2.2.1 Register and Immediate Operand Addressing Modes ...................................2-27
2.2.2.2 Memory Addressing Modes ...........................................................................2-28
2.2.2.3 I/O Port Addressing .......................................................................................2-36
2.2.2.4 Data Types Used in the 80C186 Modular Core Family .................................2-37
2.3 INTERRUPTS AND EXCEPTION HANDLING............................................................ 2-39
2.3.1 Interrupt/Exception Processing ...............................................................................2-39
2.3.1.1 Non-Maskable Interrupts ...............................................................................2-42
2.3.1.2 Maskable Interrupts .......................................................................................2-43
2.3.1.3 Exceptions .....................................................................................................2-43
CONTENTS
iv
2.3.2 Software Interrupts ..................................................................................................2-45
2.3.3 Interrupt Latency .....................................................................................................2-45
2.3.4 Interrupt Response Time ........................................................................................2-46
2.3.5 Interrupt and Exception Priority ...............................................................................2-46
CHAPTER 3
BUS INTERFACE UNIT
3.1 MULTIPLEXED ADDRESS AND DATA BUS................................................................ 3-1
3.2 ADDRESS AND DATA BUS CONCEPTS..................................................................... 3-1
3.2.1 16-Bit Data Bus .........................................................................................................3-1
3.2.2 8-Bit Data Bus ...........................................................................................................3-5
3.3 MEMORY AND I/O INTERFACES................................................................................. 3-6
3.3.1 16-Bit Bus Memory and I/O Requirements ...............................................................3-7
3.3.2 8-Bit Bus Memory and I/O Requirements .................................................................3-7
3.4 BUS CYCLE OPERATION ............................................................................................ 3-7
3.4.1 Address/Status Phase ............................................................................................3-10
3.4.2 Data Phase .............................................................................................................3-13
3.4.3 Wait States ..............................................................................................................3-13
3.4.4 Idle States ...............................................................................................................3-18
3.5 BUS CYCLES .............................................................................................................. 3-20
3.5.1 Read Bus Cycles ....................................................................................................3-20
3.5.1.1 Refresh Bus Cycles .......................................................................................3-22
3.5.2 Write Bus Cycles .....................................................................................................3-22
3.5.3 Interrupt Acknowledge Bus Cycle ...........................................................................3-25
3.5.3.1 System Design Considerations .....................................................................3-27
3.5.4 HALT Bus Cycle ......................................................................................................3-28
3.5.5 Temporarily Exiting the HALT Bus State .................................................................3-30
3.5.6 Exiting HALT ...........................................................................................................3-32
3.6 SYSTEM DESIGN ALTERNATIVES ........................................................................... 3-34
3.6.1 Buffering the Data Bus ............................................................................................3-35
3.6.2 Synchronizing Software and Hardware Events .......................................................3-37
3.6.3 Using a Locked Bus ................................................................................................3-38
3.7 MULTI-MASTER BUS SYSTEM DESIGNS................................................................. 3-39
3.7.1 Entering Bus HOLD ................................................................................................3-39
3.7.1.1 HOLD Bus Latency ........................................................................................3-40
3.7.1.2 Refresh Operation During a Bus HOLD ........................................................3-41
3.7.2 Exiting HOLD ..........................................................................................................3-43
3.8 BUS CYCLE PRIORITIES........................................................................................... 3-44
评论0
最新资源