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PSU Signal Integrity Symposium
Originally presented at PCI-SIG Developers Conference Taiwan 2023
Jason Ellison
Principal Technologist, Rohde & Schwarz
CONNECTOR AND CABLE
ASSEMBLY CHALLENGES FOR
PCIE 5.0 AND 6.0
Matt Burns
Technical Marketing Director, SAMTEC
Rohde & Schwarz
Special thanks to the following co-authors:
► Martin Stumpf, Segment Manager – High-Speed Digital Design Test at Rohde & Schwarz
► Steve Krooswyk, Senior Signal Integrity Design Engineer at Samtec
ACKNOWLEDGEMENTS
PennState SI Symposium 20232
PCIE EVOLUTION AND RESULTING CHALLENGES
3
Rohde & Schwarz
PCIe Architecture PCIe Link
PennState SI Symposium 20234
PCIE EVOLUTION
Source: PCI Express Base Specification, Revision 6.0
PCIe link is made up of one or more
full duplex lanes, each consisting of:
o 1 x differential Tx pair
o 1 x differential Rx pair
PCIe
Device
A
PCIe Link: x1, x2, x4, x8, x16 lanes
Lane 1
Lane N
PCIe
Device
B
Rohde & Schwarz
PCIE EVOLUTION
PennState SI Symposium 20235
PCIe
Revision
Year
Transfer
Rate
Encoding
Modulation
Lanes
x1 x2 x4 x8 x16
GT/s GB/s GB/s GB/s GB/s GB/s
1.0 2003 2.5 8b/10b NRZ 0.25 0.50 1.0 2.0 4.0
2.0 2007 5.0 8b/10b NRZ 0.50 1.0 2.0 4.0 8.0
3.0 2010 8.0
128b/130b
NRZ 0.98 1.97 3.94 7.88 15.8
4.0 2017 16.0
128b/130b
NRZ 1.97 3.94 7.88 15.8 31.5
5.0 2019 32.0
128b/130b
NRZ 3.94 7.88 15.8 31.5 63.0
6.0 2021 64.0 1b/1b PAM4 8.0 16.0 32.0 64.0 128.0
(GT/s x Lanes) / 8 = GB/s
剩余47页未读,继续阅读
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