PHY6252 Product Specification v1.3
Table of Contents
1 Introduction ................................................................................................................................. 1
2 Product Overview ......................................................................................................................... 2
2.1 Block Diagram ................................................................................................................................ 2
2.2 Pin Assignments and Functions ..................................................................................................... 3
2.2.1
PHY6252 (SSOP24) ........................................................................................................................ 3
2.2.1.1
Pin Assignment ...................................................................................................................... 3
2.2.1.2
Pin Functions ......................................................................................................................... 3
3 System Block ................................................................................................................................ 5
3.1 CPU ................................................................................................................................................ 5
3.2 Memory ......................................................................................................................................... 5
3.2.1
ROM .............................................................................................................................................. 7
3.2.2
SRAM ............................................................................................................................................. 7
3.2.3
FLASH ............................................................................................................................................ 7
3.2.4
eFuse ............................................................................................................................................. 7
3.2.5
Memory Address Mapping ............................................................................................................ 7
3.3 Boot and Execution Modes ........................................................................................................... 8
3.3.1
Boot Loader ................................................................................................................................... 8
3.4 Power, Clock and Reset (PCR) ....................................................................................................... 9
3.5 Power Management (POWER) ...................................................................................................... 9
3.6 Low Power Features .................................................................................................................... 11
3.6.1
Operation and Sleep States ......................................................................................................... 11
3.6.1.1
Normal State ....................................................................................................................... 11
3.6.1.2
Clock Gate State .................................................................................................................. 11
3.6.1.3
System Sleep State .............................................................................................................. 11
3.6.1.4
System Off State .................................................................................................................. 11
3.6.1.5
UVLO ................................................................................................................................... 11
3.6.2
State Transition ........................................................................................................................... 12
3.6.2.1
Entering Clock Gate State and Wake-up.............................................................................. 12
3.6.2.2
Entering Sleep/off States and Wake-up .............................................................................. 12
3.7 Interrupts ..................................................................................................................................... 12
3.8 Clock Management...................................................................................................................... 13
3.9 IOMUX ......................................................................................................................................... 14
3.10 GPIO ............................................................................................................................................. 16
3.10.1
DC Characteristics ....................................................................................................................... 16
4 Peripheral Blocks ........................................................................................................................ 17
4.1 2.4GHz Radio ............................................................................................................................... 17
4.2 Timer/Counters (TIMER) ............................................................................................................. 17
4.3 Real Time Counter (RTC) ............................................................................................................. 17
4.4 AES-ECB Encryption (ECB) ........................................................................................................... 17
4.5 Watchdog Timer (WDT) ............................................................................................................... 18
4.6 SPI (SPI0, SPI1 Two Independent Instances) ............................................................................... 18
4.7 I2C (I2c0, I2c1 Two Independent Instances) ............................................................................... 18
4.8 UART (UART0, UART1 Two Independent Instances) ................................................................... 18
4.9 DMIC/AMIC Data Path ................................................................................................................. 18
4.9.1
Filter Chain Design ...................................................................................................................... 21
