MPC8641 VxWorks BSP源码

/* sysLib.c - MPC8641 system-dependent library */ /* * Copyright (c) 2006-2007 Wind River Systems, Inc. * * The right to copy, distribute, modify or otherwise make use * of this software may be licensed only pursuant to the terms * of an applicable Wind River License agreement. */ /* modification history -------------------- 02r,26oct07,to added CPU1_INIT_START_ADR (WIND00107927) 02q,03oct07,dtr Fix coreShow. 02p,20sep07,pmr fix apigen error 02o,10sep07,pch CQ85374: fix DBAT4 setting 02n,10sep07,h_k removed vxbIntToCpuRoute() call from sysCpuEnable(). (CQ:104081) 02m,30aug07,mmi remove cpcLibP.h 02l,17aug07,h_k fixed a potential system lock issue for timebase sync. (CQ:100114). changed sysMsDelay() to call vxbMsDelay(). 02k,23jul07,h_k added DRV_TIMER_DEC_PPC is disabled case. (CQ:99195) fixed time base sync. (CQ:99192) 02j,16jul07,pmr remove direct calls to EPIC 02i,16jul07,ami removed cmdLine.c file 02h,11jul07,dtr Make PCI optional in build. 02g,06jul07,pch remove sysCpuNumGet 02g,09jul07,dtr Update AMP bootline mod. 02f,30may07,dcc added SDA initialization in sysCpu1Loop(). 02e,27may07,bwa fixed usage of CPU1CHECK when sending IPI in sysBusIntGen(). 02d,25may07,dtr Change DUAL_CORE to INCLUDE_AMP. Modify boot mode for second core Defect 95399. 02c,11may07,mmi removed vxCpuEnabled update from sysCpuEnable(), sysFlags sysBootHost and sysBootFile 02b,01may07,pmr VxBus epic cpu1 check method 02b,30apr07,pch fix UP build 02a,12apr07,pch add AMP/SMP detection and support for vxbOpenPicTimer 01z,29mar07,to SMP: enable L2 cache for 2nd core 01y,05mar07,dtr Fix AMP mode. 01x,20feb07,dtr Remove PCI from second CPU. 01w,07feb07,dtr Added PCI support. 01v,07mar07,to SMP: sysToMonitor to use cacheArchDisableFromMmu 01u,15feb07,kk added include cpcLibP.h to avoid build errors in project 01t,12jan07,pch add time base synchronization & sysCpuAvailableGet() for SMP; remove historical baggage. 01s,12dec06,tor ifdef IPI and MMU SMP calls 01r,17nov06,pch handle SMP warm reboot 01q,14nov06,tor Integrated VxBus interrupt controller 01p,15nov06,cjj sysToMonitor now resets both CPUs for SMP (temporary measure). Fixed compiler warning. 01o,09nov06,pcs Remove setting of vxCpuConfigured in sysHwInit. 01n,26oct06,to update sysCpuEnable according to the HLD 01m,20oct06,mmi update vxCpuEnabled 01l,06oct06,to made vector area cacheable and coherent 01k,21sep06,to added sysCpuInit() 01j,08sep06,dtr Mmod to PLL tables. 01i,07aug06,dtr Support DUAL_CORE over smEnd. 01h,12jun06,kk remerged with ITER9_FRZ33. 01g,06jun06,kk rolled back merge from FRZ33. 01f,28apr06,dtr Add Pixis support for dual reboot and fix sysBusIntGen for IPI. 01e,18apr06,dtr Adding IPI support. 01d,09may06,pch SPR 117691: cache/MMU global variable cleanup 01c,05may06,mig Add CPU1 IPI support 01b,04apr06,mig added SMP support 01a,05feb06,dtr written from SPS/Motorola 7448 02a. */ /* DESCRIPTION This library provides board-specific routines. The chip drivers included are: flashMem.c - 29F040 flash memory device driver. sysCacheLib.s - L1 and L2 cache lock support INCLUDE FILES: sysLib.h SEE ALSO: .pG "Configuration" */ /* includes */ #include <vxWorks.h> #include <stdio.h> #include <vme.h> #include <memLib.h> #include <cacheLib.h> #include <sysLib.h> #include "config.h" #include <string.h> #include <intLib.h> #include <logLib.h> #include <taskLib.h> #include <vxLib.h> #include <tyLib.h> #include <vmLib.h> #include <arch/ppc/mmu603Lib.h> #include <arch/ppc/vxPpcLib.h> #ifdef INCLUDE_CACHE_L2 #include "sysL2Cache.h" #endif #include <vxBusLib.h> #include <hwif/vxbus/vxBus.h> #ifdef INCLUDE_PCI_BUS #include <drv/pci/pciConfigLib.h> #include <drv/pci/pciIntLib.h> #include <drv/pci/pciAutoConfigLib.h> #include "mot85xxPci.h" #endif /* INCLUDE_PCI_BUS */ #if defined (INCLUDE_ALTIVEC) #include <altivecLib.h> #endif #ifdef INCLUDE_AMP #include <vxIpiLib.h> IMPORT int sysStartType; #endif /* INCLUDE_AMP */ IMPORT int (* _func_altivecProbeRtn) () ; /* * This must be updated after the bore bring-up specified in the SMP HLD * implemented. */ IMPORT cpuset_t vxCpuEnabled; /* defines */ #define ZERO 0 #define SYS_MODEL "HPC-NET - Freescale MPC8641D" /* globals */ /* * sysBatDesc[] is used to initialize the block address translation (BAT) * registers within the PowerPC 603/604 MMU. BAT hits take precedence * over Page Table Entry (PTE) hits and are faster. Overlap of memory * coverage by BATs and PTEs is permitted in cases where either the IBATs * or the DBATs do not provide the necessary mapping (PTEs apply to both * instruction AND data space, without distinction). * * The primary means of memory control for VxWorks is the MMU PTE support * provided by vmLib and cacheLib. Use of BAT registers will conflict * with vmLib support. User's may use BAT registers for i/o mapping and * other purposes but are cautioned that conflicts with caching and mapping * through vmLib may arise. Be aware that memory spaces mapped through a BAT * are not mapped by a PTE and any vmLib() or cacheLib() operations on such * areas will not be effective, nor will they report any error conditions. * * Note: BAT registers CANNOT be disabled - they are always active. * For example, setting them all to zero will yield four identical data * and instruction memory spaces starting at local address zero, each 128KB * in size, and each set as write-back and cache-enabled. Hence, the BAT regs * MUST be configured carefully. * * With this in mind, it is recommended that the BAT registers be used * to map LARGE memory areas external to the processor if possible. * If not possible, map sections of high RAM and/or PROM space where * fine grained control of memory access is not needed. This has the * beneficial effects of reducing PTE table size (8 bytes per 4k page) * and increasing the speed of access to the largest possible memory space. * Use the PTE table only for memory which needs fine grained (4KB pages) * control or which is too small to be mapped by the BAT regs. * * The BAT configuration for 4xx/6xx-based PPC boards is as follows: * All BATs point to PROM/FLASH memory so that end customer may configure * them as required. * * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments] */ UINT32 sysBatDesc [] = { /* I BAT 0 */ ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_8M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT), /* I BAT 1 */ 0, 0, /* I BAT 2 */ 0, 0, /* I BAT 3 */ 0, 0, /* D BAT 0 */ ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_8M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT), /* D BAT 1 */ ((CCSBAR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((CCSBAR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 2 */ ((0x10000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((0x10000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_MEM_COHERENT), /* D BAT 3 */ #ifdef INCLUDE_PCI_BUS ((PCI_MEM_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP), ((PCI_MEM_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED) #else 0, 0 #endif /* These entries are for the I/D BAT's (4-7) on the MPC755/745x/8641. They should be defined in the following order. IBAT4U, IBAT4L, IBAT5U, IBAT5L, IBAT6U, IBAT6L, IBAT7U, IBAT7L, DBAT4U, DBAT4L, DBAT5U, DBAT5L, DBAT6U, DBAT6L, DBAT7U, DBAT7L, */ , /* I BAT 4 */ 0, 0, /* I BAT 5 */ 0, 0,