AUDIO相关接口如I2S协议,AC97,SPDIF等介绍

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AUDIO

I2S协议

AC97

SPDIF

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在电子设备尤其是音频系统中，接口的选择和理解至关重要。这里我们着重探讨三个常见的AUDIO接口：I2S协议、AC97以及SPDIF。 I2S（Integrated Interchip Sound）协议是一种专为数字音频数据传输设计的接口标准。它由飞利浦公司开发，用于连接数字音频源（如CD播放器）和数字音频处理器（如DAC解码器）。I2S接口通常包括数据线（如主时钟MCLK、帧时钟BCLK、数据线DATA）和一个选择左或右声道的信号线（LRCK）。I2S的优势在于其高效的数据传输能力，能够确保音频数据的精确无损传输，适用于高质量音频系统。 AC97是Audio Codec '97的简称，是由英特尔、Creative Labs、Analog Devices、Lucent Technologies和Microsoft等公司联合制定的一套音频编解码器规范。AC97主要用于集成声卡，它定义了数字信号与模拟信号之间的转换方式，支持立体声和环绕声。AC97规范包括两部分：Codec（编解码器）和控制集线器（Control Hub），其中Codec负责音频数据的编码和解码，而控制集线器则管理各种音频设置和功能。再来看SPDIF（Sony/Philips Digital Interface Format），这是索尼和飞利浦共同制定的一种数字音频接口标准，用于传输未压缩的立体声数字音频信号。SPDIF分为同轴和光纤两种形式，其中同轴SPDIF使用BNC或RCA接口，而光纤SPDIF使用TOSLINK接口。SPDIF的优势在于其抗干扰能力强，传输质量高，且兼容性好，能与多种数字音频设备无缝对接。在实际应用中，AC97常被用作集成在主板上的低成本音频解决方案，而I2S和SPDIF则更多地出现在高端音频设备中，提供更高质量的音频输出。例如，I2S常用于Hi-Fi音乐播放器和专业音频设备中，SPDIF则广泛应用于家庭影院系统和音响设备。了解这些接口的工作原理和特点，对于设计和选择合适的音频系统至关重要。例如，在搭建多声道音频系统时，可能需要使用SPDIF来实现数字音频的无损传输；而在开发嵌入式音频设备时，AC97的低功耗和成本效益可能是首选；而I2S则适用于追求高音质的发烧友，因为它可以实现精确的时钟同步，从而提供更好的音频表现。理解这些音频接口不仅可以帮助我们更好地理解和配置音频系统，还能够指导我们在硬件设计和选购中做出更为明智的决策。无论是对电子工程师还是普通用户，掌握这些知识都能提升我们对音频设备的理解，从而享受更优质的音乐体验。

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audio_codec.rar （10个子文件）

AC97和HD规范简介前置音频接口的连接教程_随缘斋.mht 1.81MB

codece接口_AC97接口_I2S接口_PCM接口.txt 1KB

I2S

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S-PDIF接口介绍？ - tcltest 常见问题应用软件问题 - TCL电脑科技 - 53IQ自助服务.mht 214KB

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小议音频数字接口Ｓ／ＰＤＩＦ.mht 159KB

I2SBUS.pdf 60KB

声卡中的AC97是什么意思_百度知道.mht 100KB

电脑硬件术语介绍雨林木风交流论坛[BBS_YlmF_CoM] - 真正属于菜鸟的网络天堂！.mht 424KB

AC97声卡_百度百科.mht 86KB

Philips Semiconductors

S bus specification

February 1986 Revised: June 5, 1996

1.0 INTRODUCTION

Many digital audio systems are being introduced into the consumer

audio market, including compact disc, digital audio tape, digital

sound processors, and digital TV-sound. The digital audio signals in

these systems are being processed by a number of (V)LSI ICs,

such as:

•A/D and D/A converters;

•digital signal processors;

•error correction for compact disc and digital recording;

•digital filters;

• digital input/output interfaces.

Standardized communication structures are vital for both the

equipment and the IC manufacturer, because they increase system

flexibility. To this end, we have developed the inter-IC sound (I

bus – a serial link especially for digital audio.

2.0 BASIC SERIAL BUS REQUIREMENTS

The bus has only to handle audio data, while the other signals, such

as sub-coding and control, are transferred separately. To minimize

the number of pins required and to keep wiring simple, a 3-line serial

bus is used consisting of a line for two time-multiplexed data

channels, a word select line and a clock line.

Since the transmitter and receiver have the same clock signal for

data transmission, the transmitter as the master, has to generate the

bit clock, word-select signal and data. In complex systems however,

there may be several transmitters and receivers, which makes it

difficult to define the master. In such systems, there is usually a

system master controlling digital audio data-flow between the

various ICs. Transmitters then, have to generate data under the

control of an external clock, and so act as a slave. Figure 1

illustrates some simple system configurations and the basic

interface timing. Note that the system master can be combined with

a transmitter or receiver, and it may be enabled or disabled under

software control or by pin programming.

TRANSMITTER

clock SCK

word select WS

data SD

RECEIVER

TRANSMITTER = MASTER

TRANSMITTER

SCK

RECEIVER

RECEIVER = MASTER

TRANSMITTER

SCK

RECEIVER

CONTROLLER = MASTER

CONTROLLER

SCK

WORD n–1

RIGHT CHANNEL

WORD n+1

RIGHT CHANNEL

WORD n

LEFT CHANNEL

LSB MSBMSB

SN00119

Figure 1. Simple System Configurations and Basic Interface Timing

Philips Semiconductors

S bus specification

February 1986

3.0 THE I

S BUS

As shown in Figure 1, the bus has three lines:

•continuous serial clock (SCK);

•word select (WS);

•serial data (SD);

and the device generating SCK and WS is the master.

3.1 Serial Data

Serial data is transmitted in two’s complement with the MSB first.

The MSB is transmitted first because the transmitter and receiver

may have different word lengths. It isn’t necessary for the transmitter

to know how many bits the receiver can handle, nor does the

receiver need to know how many bits are being transmitted.

When the system word length is greater than the transmitter word

length, the word is truncated (least significant data bits are set to ‘0’)

for data transmission. If the receiver is sent more bits than its word

length, the bits after the LSB are ignored. On the other hand, if the

receiver is sent fewer bits than its word length, the missing bits are

set to zero internally. And so, the MSB has a fixed position, whereas

the position of the LSB depends on the word length. The transmitter

always sends the MSB of the next word one clock period after the

WS changes.

Serial data sent by the transmitter may be synchronized with either

the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of

the clock signal. However, the serial data must be latched into the

receiver on the leading edge of the serial clock signal, and so there

are some restrictions when transmitting data that is synchronized

with the leading edge (see Figure 2 and Table 1).

3.2 Word Select

The word select line indicates the channel being transmitted:

•WS = 0; channel 1 (left);

•WS = 1; channel 2 (right).

WS may change either on a trailing or leading edge of the serial

clock, but it doesn’t need to be symmetrical. In the slave, this signal

is latched on the leading edge of the clock signal. The WS line

changes one clock period before the MSB is transmitted. This allows

the slave transmitter to derive synchronous timing of the serial data

that will be set up for transmission. Furthermore, it enables the

receiver to store the previous word and clear the input for the next

word (see Figure 1).

4.0 TIMING

In the I

S format, any device can act as the system master by

providing the necessary clock signals. A slave will usually derive its

internal clock signal from an external clock input. This means, taking

into account the propagation delays between master clock and the

data and/or word-select signals, that the total delay is simply the

sum of:

•the delay between the external (master) clock and the slave’s

internal clock; and

•the delay between the internal clock and the data and/or

word-select signals.

For data and word-select inputs, the external to internal clock delay

is of no consequence because it only lengthens the effective set-up

time (see Figure 2). The major part of the time margin is to

accommodate the difference between the propagation delay of the

transmitter, and the time required to set up the receiver.

All timing requirements are specified relative to the clock period or to

the minimum allowed clock period of a device. This means that

higher data rates can be used in the future.

and

SCK

RC*

≥ 0.35T t

≥ 0.35T

= 2.0V

= 0.8V

htr

≥ 0

dtr

≤ 0.8T

T = clock period

= minimum allowed clock period for transmitter

T>T

∗ t

is only relevant for transmitters in slave mode.

SN00120

Figure 2. Timing for I

S Transmitter

Philips Semiconductors

S bus specification

February 1986

and

SCK

≥ 0.35T t

≥ 0.35

= 2.0V

= 0.8V

T = clock period

= minimum allowed clock period for transmitter

T>T

≥ 0.2T t

≥ 0

SN00121

Figure 3. Timing for I

S Receiver

Note that the times given in both Figures 2 and 3 are defined by the transmitter speed. The specification of the receiver has to be able to match

the performance of the transmitter

Example: Master transmitter with data rate of 2.5MHz (±10%) (all values in ns)

MIN TYP MAX CONDITION

clock period T 360 400 440 T

= 360

clock HIGH t

160 min > 0.35T = 140 (at typical data rate)

clock LOW t

160 min > 0.35T = 140 (at typical data rate)

delay t

dtr

300 max < 0.80T = 320 (at typical data rate)

hold time t

htr

100 min > 0

clock rise-time t

60 max > 0.15T

= 54 (only relevant in slave mode)

Example: Slave receiver with data rate of 2.5MHz (±10%) (all values in ns)

MIN TYP MAX CONDITION

clock period T 360 400 440 T

= 360

clock HIGH t

110 min < 0.35T = 126

clock LOW t

110 min < 0.35T = 126

set-up time t

60 min < 0.20T = 72

hold time t

htr

0 min < 0

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zpg189

2011-11-07

是一些网页，不过有一些用，谢谢。

AUDIO相关接口如I2S协议,AC97,SPDIF等介绍

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