CompactPCI
®
Core Specification PICMG 2.0 D3.0 9/24/99
iii
Draft for PICMG Executive Approval
Do not specify or claim conformance to this specification - Not for Distribution
Contents
1 OVERVIEW ........................................................................................................................................ 9
1.1 C
OMPACTPCI OBJECTIVES................................................................................................................ 9
1.2 B
ACKGROUND AND TERMINOLOGY................................................................................................... 9
1.3 D
ESIRED AUDIENCE .......................................................................................................................... 9
1.4 C
OMPACTPCI FEATURES ................................................................................................................ 10
1.5 A
PPLICABLE DOCUMENTS ............................................................................................................... 10
1.6 A
DMINISTRATION ............................................................................................................................ 11
1.7 N
AME AND LOGO USAGE................................................................................................................ 12
2 FEATURE SET ................................................................................................................................. 13
2.1 F
ORM FACTOR................................................................................................................................. 13
2.2 C
ONNECTOR .................................................................................................................................... 15
2.3 M
ODULARITY .................................................................................................................................. 16
2.4 H
OT SWAP CAPABILITY ................................................................................................................... 16
3 ELECTRICAL REQUIREMENTS ................................................................................................. 17
3.1 B
OARD DESIGN RULES .................................................................................................................... 17
3.1.1 Decoupling Requirements..................................................................................................... 17
3.1.2 CompactPCI Signal Additions .............................................................................................. 18
3.1.3 CompactPCI Stub Termination............................................................................................. 18
3.1.4 Peripheral Board Signal Stub Length................................................................................... 18
3.1.5 Characteristic Impedance..................................................................................................... 19
3.1.6 System Slot Board Signal Stub Length.................................................................................. 19
3.1.7 Peripheral Board PCI Clock Signal Length ......................................................................... 19
3.1.8 Pull-Up Location .................................................................................................................. 19
3.1.9 Board Connector Shield Requirements................................................................................. 20
3.2 B
ACKPLANE DESIGN RULES ............................................................................................................ 21
3.2.1 Characteristic Impedance..................................................................................................... 21
3.2.2 Eight-Slot Backplane Termination........................................................................................ 21
3.2.3 Signaling Environment ......................................................................................................... 22
3.2.4 IDSEL Assignment ................................................................................................................ 22
3.2.5 REQ#/GNT# Assignment ...................................................................................................... 23
3.2.6 PCI Interrupt Binding........................................................................................................... 24
3.2.7 CompactPCI Signal Additions .............................................................................................. 25
3.2.8 Power Distribution................................................................................................................ 28
3.2.9 Power Decoupling ................................................................................................................ 30
3.2.10 Healthy (Healthy#) ............................................................................................................... 31
3.3 33 MH
Z PCI CLOCK DISTRIBUTION ................................................................................................ 31
3.3.1 Backplane Clock Routing Design Rules................................................................................ 32
3.3.2 System Slot Board Clock Routing Design Rules ................................................................... 32
3.4 64-B
IT DESIGN RULES..................................................................................................................... 33
3.5 66 MH
Z ELECTRICAL REQUIREMENTS ............................................................................................ 35
3.5.1 66 MHz Board Design Rules................................................................................................. 35
3.5.2 66 MHz System Board Design Rules..................................................................................... 35
3.5.3 66MHz Backplane Design Rules........................................................................................... 35
3.5.4 66MHz PCI Clock Distribution............................................................................................. 35
3.5.5 66 MHz System Slot Board Clock Routing Design Rules...................................................... 36
3.5.6 66 MHz Hot Swap................................................................................................................. 37
3.6 S
YSTEM AND BOARD GROUNDING .................................................................................................. 37
3.6.1 Board Front Panel Grounding Requirements....................................................................... 37
3.6.2 Backplane Grounding Requirements .................................................................................... 37
3.7 C
OMPACTPCI BUFFER MODELS...................................................................................................... 37
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ruyu33262012-08-14原始资料，属于工具书，必须具备的参考资料。做CPCI架构开发的，必须具备此资料。
