Hierarchical_State_Machine 源代码

For details refer to the article on Hierarchical State Machines In conventional state machine design, all states are considered at the same level. The design does not capture the commonality that exists among states. In real life, many states handle most messages in similar fashion and differ only in handling of few key messages. Even when the actual handling differs, there is still some commonality. Hierarchical state machine design captures the commonality by organizing the states as a hierarchy. The states at the higher level in hierarchy perform the common message handling, while the lower level states inherit the commonality from higher level ones and perform the state specific functions. This examples explores hierarchichal state machines using an example of a hardware unit that can be in the following states: •Inservice state ◦Active state ◦Standby state •Out_Of_Service ◦Suspect state ◦Failed state Definition at line 32 of file Hierarchical_State_Machine.h.