SNUG San Jose 2004 4 The PLI Is Dead (maybe)—Long Live The DPI
must begin with a dollar sign ( $ ). A task in Verilog is analogous to a subroutine. When a task is
called, the simulator’s instruction flow branches to a subroutine. Upon completion of the task, the
instruction flow returns back to the instruction following the task call. Verilog tasks do not return
values, but can have input, output and inout (bidirectional) formal arguments. A function in
Verilog is analogous to functions in most languages. When a function is called, it executes a set of
instructions, and then returns a value back to the statement that called the function. Verilog tasks
and functions can be defined as part of the Verilog language.
Using the Verilog PLI, a programmer must first define a system task function name, such as
$sine. The programmer then creates a C function referred to as a calltf routine, which will be
associated with the $sine task/function name. When simulation executes the statement with the
$sine system function call, the simulator calls the calltf routine associated with $sine. This calltf
routine is a layer between $sine and the sin function in the C math library. The arguments to
$sine are not passed directly to the calltf routine. Instead, the calltf routine must call special PLI
functions from a PLI library to read the input argument of $sine. The calltf routine can then call
the sin function, passing the input to the function. The calltf routine will receive the return value
from the sin function, and then call another special PLI function to write this return value back to
the $sine function. A final step when using the Verilog PLI is to bind the user-defined system
task/function name with the user-defined calltf routine. This step is different for each simulator,
and can range from editing a special table file to editing and compiling a complex C language file.
The PLI libraries allow a calltf routine to do more than just work with the arguments of a system
task or function. The libraries also allow a calltf application to search for objects in the simulation
data structure, modify delays and logic values in the data structure, and synchronize to simulation
activity and simulation time.
3.2 The evolution of the Verilog PLI
The Verilog PLI was originally developed in the mid to late 1980s as a proprietary interface to the
Gateway Design Automation Verilog-XL simulator product (now owned by Cadence Design
Systems). Gateway developed the PLI to satisfy two fundamental needs: First was to allow
Verilog-XL users a mechanism to use the C language for tasks such as file I/O. Second was to
provide a mechanism for ASIC foundries to analyze the usage of their standard cell libraries in
order to calculate accurate propagation delays within each cell instance. From these two
fundamental intents, the usage of the Verilog PLI has expanded in many ways. Common
applications of the Verilog PLI in today’s engineering environments include: commercial and
proprietary waveform viewers, commercial and proprietary design debug utilities, RAM/ROM
program loaders, scan chain vector loaders, custom file readers and writers, power analysis,
circuit tracing, C model interfaces, co-simulation environments, parallel process distribution, and
much, much more. The ways in which the PLI can be used to extend Verilog simulators is limited
only by the imagination of programmers.
The following paragraphs introduce the several generations of the Verilog PLI.
1985 — the TF interface. The first generation of the Verilog PLI is referred to as the Task/
Function interface, or TF interface. The TF interface comprises a set of C language functions
defined in a library file called verisuer.h. These C functions are typically referred to as the TF
routines. The primary purpose of the TF routines is to allow task/function arguments to be passed